From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yoshinori Sato Date: Sun, 12 Jun 2016 06:54:34 +0000 Subject: [PATCH v2 16/17] sh: I/O DATA HDL-U (a.k.a. landisk) Device Tree Message-Id: <1465714475-24111-17-git-send-email-ysato@users.sourceforge.jp> List-Id: References: <1465714475-24111-1-git-send-email-ysato@users.sourceforge.jp> In-Reply-To: <1465714475-24111-1-git-send-email-ysato@users.sourceforge.jp> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Yoshinori Sato Signed-off-by: Yoshinori Sato --- arch/sh/boot/dts/landisk.dts | 150 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 arch/sh/boot/dts/landisk.dts diff --git a/arch/sh/boot/dts/landisk.dts b/arch/sh/boot/dts/landisk.dts new file mode 100644 index 0000000..23396a0 --- /dev/null +++ b/arch/sh/boot/dts/landisk.dts @@ -0,0 +1,150 @@ +#include + +/dts-v1/; +/ { + model = "I/O DATA HDL-U"; + compatible = "iodata,hdl-u"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&shintc>; + chosen { + stdout-path = &sci1; + bootargs = "console=ttySC1,115200"; + }; + aliases { + serial0 = &sci0; + serial1 = &sci1; + }; + + oclk: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <22222222>; + }; + pllclk: pllclk { + compatible = "renesas,sh7750-pll-clock"; + clocks = <&oclk>; + #clock-cells = <0>; + renesas,mult = <12>; + reg = <0xffc00000 2>, <0xffc00008 4>; + }; + iclk: iclk { + compatible = "renesas,sh7750-div-clock"; + clocks = <&pllclk>; + #clock-cells = <0>; + reg = <0xffc00000 2>; + renesas,offset = <6>; + clock-output-names = "ick"; + }; + bclk: bclk { + compatible = "renesas,sh7750-div-clock"; + clocks = <&pllclk>; + #clock-cells = <0>; + reg = <0xffc00000 2>; + renesas,offset = <3>; + clock-output-names = "bck"; + }; + fclk: fclk { + compatible = "renesas,sh7750-div-clock"; + clocks = <&pllclk>; + #clock-cells = <0>; + reg = <0xffc00000 2>; + renesas,offset = <0>; + clock-output-names = "fck"; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "renesas,sh4", "renesas,sh"; + clock-frequency = <266666666>; + }; + }; + memory@0c000000 { + device_type = "memory"; + reg = <0x0c000000 0x4000000>; + }; + shintc: interrupt-controller@ffd00000 { + compatible = "renesas,sh7751-intc"; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0xffd00000 14>, <0xfe080000 128>; + + }; + cpldintc: cpld@b0000000 { + compatible = "iodata,landisk-intc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xb0000000 8>; + interrupt-map=<0 &shintc 0 0>, <1 &shintc 1 0>, + <2 &shintc 2 0>, <3 &shintc 3 0>, + <4 &shintc 4 0>, <5 &shintc 5 0>, + <6 &shintc 6 0>, <7 &shintc 7 0>; + }; + sci0: serial@ffe00000 { + compatible = "renesas,scif"; + reg = <0xffe00000 0x20>; + interrupts = ; + clocks = <&fclk>; + clock-names = "fck"; + }; + sci1: serial@ffe80000 { + compatible = "renesas,scif"; + reg = <0xffe80000 0x100>; + interrupts = ; + clocks = <&fclk>; + clock-names = "fck"; + }; + tmu: timer@ffd80000 { + compatible = "renesas,tmu"; + reg = <0xffd80000 12>; + interrupts = ; + clocks = <&fclk>; + clock-names = "fck"; + renesas,channels-mask = <0x03>; + }; + + pci: pci-controller@fe200000 { + compatible = "renesas,sh7751-pci", "iodata,landisk"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x02000000 0x00000000 0xfd000000 0xfd000000 0x00000000 0x01000000>, + <0x01000000 0x00000000 0xfe240000 0x00000000 0x00000000 0x00040000>; + reg = <0xfe200000 0x0400>, + <0x0c000000 0x04000000>, + <0xff800000 0x0030>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x1800 0 7>; + interrupt-map = <0x0000 0 1 &cpldintc evt2irq(0x2a0) 0 + 0x0000 0 2 &cpldintc evt2irq(0x2c0) 0 + 0x0000 0 3 &cpldintc evt2irq(0x2e0) 0 + 0x0000 0 4 &cpldintc evt2irq(0x300) 0 + + 0x0800 0 1 &cpldintc evt2irq(0x2c0) 0 + 0x0800 0 2 &cpldintc evt2irq(0x2e0) 0 + 0x0800 0 3 &cpldintc evt2irq(0x300) 0 + 0x0800 0 4 &cpldintc evt2irq(0x2a0) 0 + + 0x1000 0 1 &cpldintc evt2irq(0x2e0) 0 + 0x1000 0 2 &cpldintc evt2irq(0x300) 0 + 0x1000 0 3 &cpldintc evt2irq(0x2a0) 0 + 0x1000 0 4 &cpldintc evt2irq(0x2c0) 0 + + 0x1800 0 1 &cpldintc evt2irq(0x300) 0 + 0x1800 0 2 &cpldintc evt2irq(0x2a0) 0 + 0x1800 0 3 &cpldintc evt2irq(0x2c0) 0 + 0x1800 0 4 &cpldintc evt2irq(0x2e0) 0>; + }; +}; -- 2.7.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753437AbcFLGz1 (ORCPT ); Sun, 12 Jun 2016 02:55:27 -0400 Received: from mail1.asahi-net.or.jp ([202.224.39.197]:15545 "EHLO mail1.asahi-net.or.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753045AbcFLGyn (ORCPT ); Sun, 12 Jun 2016 02:54:43 -0400 From: Yoshinori Sato To: linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Yoshinori Sato Subject: [PATCH v2 16/17] sh: I/O DATA HDL-U (a.k.a. landisk) Device Tree Date: Sun, 12 Jun 2016 15:54:34 +0900 Message-Id: <1465714475-24111-17-git-send-email-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1465714475-24111-1-git-send-email-ysato@users.sourceforge.jp> References: <1465714475-24111-1-git-send-email-ysato@users.sourceforge.jp> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Signed-off-by: Yoshinori Sato --- arch/sh/boot/dts/landisk.dts | 150 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 arch/sh/boot/dts/landisk.dts diff --git a/arch/sh/boot/dts/landisk.dts b/arch/sh/boot/dts/landisk.dts new file mode 100644 index 0000000..23396a0 --- /dev/null +++ b/arch/sh/boot/dts/landisk.dts @@ -0,0 +1,150 @@ +#include + +/dts-v1/; +/ { + model = "I/O DATA HDL-U"; + compatible = "iodata,hdl-u"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&shintc>; + chosen { + stdout-path = &sci1; + bootargs = "console=ttySC1,115200"; + }; + aliases { + serial0 = &sci0; + serial1 = &sci1; + }; + + oclk: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <22222222>; + }; + pllclk: pllclk { + compatible = "renesas,sh7750-pll-clock"; + clocks = <&oclk>; + #clock-cells = <0>; + renesas,mult = <12>; + reg = <0xffc00000 2>, <0xffc00008 4>; + }; + iclk: iclk { + compatible = "renesas,sh7750-div-clock"; + clocks = <&pllclk>; + #clock-cells = <0>; + reg = <0xffc00000 2>; + renesas,offset = <6>; + clock-output-names = "ick"; + }; + bclk: bclk { + compatible = "renesas,sh7750-div-clock"; + clocks = <&pllclk>; + #clock-cells = <0>; + reg = <0xffc00000 2>; + renesas,offset = <3>; + clock-output-names = "bck"; + }; + fclk: fclk { + compatible = "renesas,sh7750-div-clock"; + clocks = <&pllclk>; + #clock-cells = <0>; + reg = <0xffc00000 2>; + renesas,offset = <0>; + clock-output-names = "fck"; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "renesas,sh4", "renesas,sh"; + clock-frequency = <266666666>; + }; + }; + memory@0c000000 { + device_type = "memory"; + reg = <0x0c000000 0x4000000>; + }; + shintc: interrupt-controller@ffd00000 { + compatible = "renesas,sh7751-intc"; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0xffd00000 14>, <0xfe080000 128>; + + }; + cpldintc: cpld@b0000000 { + compatible = "iodata,landisk-intc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xb0000000 8>; + interrupt-map=<0 &shintc 0 0>, <1 &shintc 1 0>, + <2 &shintc 2 0>, <3 &shintc 3 0>, + <4 &shintc 4 0>, <5 &shintc 5 0>, + <6 &shintc 6 0>, <7 &shintc 7 0>; + }; + sci0: serial@ffe00000 { + compatible = "renesas,scif"; + reg = <0xffe00000 0x20>; + interrupts = ; + clocks = <&fclk>; + clock-names = "fck"; + }; + sci1: serial@ffe80000 { + compatible = "renesas,scif"; + reg = <0xffe80000 0x100>; + interrupts = ; + clocks = <&fclk>; + clock-names = "fck"; + }; + tmu: timer@ffd80000 { + compatible = "renesas,tmu"; + reg = <0xffd80000 12>; + interrupts = ; + clocks = <&fclk>; + clock-names = "fck"; + renesas,channels-mask = <0x03>; + }; + + pci: pci-controller@fe200000 { + compatible = "renesas,sh7751-pci", "iodata,landisk"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x02000000 0x00000000 0xfd000000 0xfd000000 0x00000000 0x01000000>, + <0x01000000 0x00000000 0xfe240000 0x00000000 0x00000000 0x00040000>; + reg = <0xfe200000 0x0400>, + <0x0c000000 0x04000000>, + <0xff800000 0x0030>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x1800 0 7>; + interrupt-map = <0x0000 0 1 &cpldintc evt2irq(0x2a0) 0 + 0x0000 0 2 &cpldintc evt2irq(0x2c0) 0 + 0x0000 0 3 &cpldintc evt2irq(0x2e0) 0 + 0x0000 0 4 &cpldintc evt2irq(0x300) 0 + + 0x0800 0 1 &cpldintc evt2irq(0x2c0) 0 + 0x0800 0 2 &cpldintc evt2irq(0x2e0) 0 + 0x0800 0 3 &cpldintc evt2irq(0x300) 0 + 0x0800 0 4 &cpldintc evt2irq(0x2a0) 0 + + 0x1000 0 1 &cpldintc evt2irq(0x2e0) 0 + 0x1000 0 2 &cpldintc evt2irq(0x300) 0 + 0x1000 0 3 &cpldintc evt2irq(0x2a0) 0 + 0x1000 0 4 &cpldintc evt2irq(0x2c0) 0 + + 0x1800 0 1 &cpldintc evt2irq(0x300) 0 + 0x1800 0 2 &cpldintc evt2irq(0x2a0) 0 + 0x1800 0 3 &cpldintc evt2irq(0x2c0) 0 + 0x1800 0 4 &cpldintc evt2irq(0x2e0) 0>; + }; +}; -- 2.7.0