From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42510) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCp6Z-0003Iy-HD for qemu-devel@nongnu.org; Tue, 14 Jun 2016 10:14:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bCp6X-0007zh-ED for qemu-devel@nongnu.org; Tue, 14 Jun 2016 10:14:10 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:57706) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCp6X-0007yr-6w for qemu-devel@nongnu.org; Tue, 14 Jun 2016 10:14:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1bCp6V-0006D9-U2 for qemu-devel@nongnu.org; Tue, 14 Jun 2016 15:14:07 +0100 From: Peter Maydell Date: Tue, 14 Jun 2016 15:13:39 +0100 Message-Id: <1465913645-19346-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1465913645-19346-1-git-send-email-peter.maydell@linaro.org> References: <1465913645-19346-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 04/30] target-arm: Fix reset and migration of TTBCR(S) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Commit 6459b94c26dd666badb3 broke reset and migration of the AArch32 TTBCR(S) register if the guest used non-LPAE page tables. This is because the AArch32 TTBCR register definition is marked as ARM_CP_ALIAS, meaning that the AArch64 variant has to handle migration and reset. Although AArch64 TCR_EL3 doesn't need to care about the mask and base_mask fields, AArch32 may do so, and so we must use the special TTBCR reset and raw write functions to ensure they are set correctly. This doesn't affect TCR_EL2, because the AArch32 equivalent of that is HTCR, which never uses the non-LPAE page table variant. Signed-off-by: Peter Maydell Reported-by: Pranith Kumar Reviewed-by: Sergey Fedorov Message-id: 1465488181-31977-1-git-send-email-peter.maydell@linaro.org --- target-arm/helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 862e780..c9730d6 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3765,8 +3765,11 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, .access = PL3_RW, /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask + * we must provide a .raw_writefn and .resetfn because we handle + * reset and migration for the AArch32 TTBCR(S), which might be + * using mask and base_mask. */ + .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, -- 1.9.1