From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52595) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bGK5Y-000054-UU for qemu-devel@nongnu.org; Fri, 24 Jun 2016 01:55:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bGK5X-0005pu-Mj for qemu-devel@nongnu.org; Fri, 24 Jun 2016 01:55:36 -0400 Received: from mx1.redhat.com ([209.132.183.28]:35205) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bGK5X-0005pp-HD for qemu-devel@nongnu.org; Fri, 24 Jun 2016 01:55:35 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 10278633EB for ; Fri, 24 Jun 2016 05:55:35 +0000 (UTC) Message-ID: <1466747733.16435.7.camel@redhat.com> From: Gerd Hoffmann Date: Fri, 24 Jun 2016 07:55:33 +0200 In-Reply-To: <20160623193648-mutt-send-email-mst@redhat.com> References: <20160617151900.GE18662@thinpad.lan.raisama.net> <20160617154905.GH18662@thinpad.lan.raisama.net> <20160621194440.GN17952@thinpad.lan.raisama.net> <9b76415a-23e6-3ded-4dbc-42838cc164b0@redhat.com> <20160622142414.GI30202@redhat.com> <20160623014216-mutt-send-email-mst@redhat.com> <20160622232308.GQ30202@redhat.com> <20160623024400-mutt-send-email-mst@redhat.com> <1466671203.26189.35.camel@redhat.com> <20160623193648-mutt-send-email-mst@redhat.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Mime-Version: 1.0 Subject: Re: [Qemu-devel] Default for phys-addr-bits? (was Re: [PATCH 4/5] x86: Allow physical address bits to be set) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Andrea Arcangeli , Marcel Apfelbaum , Paolo Bonzini , qemu-devel@nongnu.org, Eduardo Habkost , "Dr. David Alan Gilbert" On Do, 2016-06-23 at 19:38 +0300, Michael S. Tsirkin wrote: > On Thu, Jun 23, 2016 at 10:40:03AM +0200, Gerd Hoffmann wrote: > > Hi, > >=20 > > > > Well the crash of guest phys bits > host phys bits, should be easy = to > > > > reproduce by booting a 65GB guest on a 64GB RAM + 2GB swap host wit= h > > > > 36 host phys bits using the upstream qemu that forces the guest phy= s > > > > bits to 40. > > >=20 > > > So you supply more RAM than host can address, and guest crashes? > >=20 > > Yep. The only reason we don't see this happening in practice is that > > it's probably next to impossible to find a machine which has (a) only 3= 6 > > physical address lines and (b) allows to plug that much RAM. > >=20 > > > Why are we worried about it? > >=20 > > It's more a issue with pci ressources. In theory seabios/edk2 could go > > figure how big the physical address space is, then map 64bit pci bars a= s > > high as possible, thereby making stuff like etc/reserved-memory-end in > > fw_cfg unnecessary. > >=20 > > But with qemu saying 40 phys bits are available even if they are not > > this approach isn't going to fly ... > >=20 > > cheers, > > Gerd >=20 > Nah, x86 guests really need to go by _CRS. Yep, we can implement the "soft-phys-bits" that way. > bios doesn't want to parse that > so it can go by some fw cfg file instead. firmware can't use it anyway because the firmware first maps the bars, the loads acpi tables (while qemu generates _CRS entries according to the bios mappings). > Going by phys bits won't work on old qemu so I don't believe it's > practical. Indeed, so I guess we'll have to stick to the current approach of mapping 64bit bars above ram (or etc/reserved-memory-end if present). cheers, Gerd