From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59056) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHboG-0006n1-DA for qemu-devel@nongnu.org; Mon, 27 Jun 2016 15:03:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHboB-0008N5-5s for qemu-devel@nongnu.org; Mon, 27 Jun 2016 15:03:04 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:52736) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHbo8-0008CL-Rt for qemu-devel@nongnu.org; Mon, 27 Jun 2016 15:02:59 -0400 From: "Emilio G. Cota" Date: Mon, 27 Jun 2016 15:02:10 -0400 Message-Id: <1467054136-10430-25-git-send-email-cota@braap.org> In-Reply-To: <1467054136-10430-1-git-send-email-cota@braap.org> References: <1467054136-10430-1-git-send-email-cota@braap.org> Subject: [Qemu-devel] [RFC 24/30] target-arm: emulate SWP with atomic_xchg helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU Developers , MTTCG Devel Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Richard Henderson , Sergey Fedorov , Alvise Rigo , Peter Maydell Signed-off-by: Emilio G. Cota --- target-arm/translate.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 0d4a1a9..b177388 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -8783,18 +8783,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* SWP instruction */ rm = (insn) & 0xf; - /* ??? This is not really atomic. However we know - we never have multiple CPUs running in parallel, - so it is good enough. */ addr = load_reg(s, rn); tmp = load_reg(s, rm); tmp2 = tcg_temp_new_i32(); if (insn & (1 << 22)) { - gen_aa32_ld8u(s, tmp2, addr, get_mem_index(s)); - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); + gen_helper_atomic_xchgb(tmp2, cpu_env, addr, tmp); } else { - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_helper_atomic_xchgl(tmp2, cpu_env, addr, tmp); } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); -- 2.5.0