From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bK2rO-0007VV-3E for qemu-devel@nongnu.org; Mon, 04 Jul 2016 08:20:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bK2rI-0003v0-1c for qemu-devel@nongnu.org; Mon, 04 Jul 2016 08:20:21 -0400 Received: from 11.mo3.mail-out.ovh.net ([87.98.184.158]:56007) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bK2rH-0003ul-Om for qemu-devel@nongnu.org; Mon, 04 Jul 2016 08:20:15 -0400 Received: from player761.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id D67E7FFBEC4 for ; Mon, 4 Jul 2016 14:20:14 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 4 Jul 2016 14:18:56 +0200 Message-Id: <1467634738-28642-6-git-send-email-clg@kaod.org> In-Reply-To: <1467634738-28642-1-git-send-email-clg@kaod.org> References: <1467634738-28642-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 5/7] ast2400: handle SPI flash Command mode (read only) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , Peter Crosthwaite Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Andrew Jeffery , mar.krzeminski@gmail.com, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To handle memory accesses when the SPI flash slave is configured in Command mode, let's change the memory region of the SPI flash object to a ROM memory region (like the pflash_cfi* object). The m25p80 flash object creation is changed accordingly to use the new memory region as a storage. Only read only accesses are handled. Supporting write accesses would demand using internal routines of the m25p80 flash model. This is not required for the moment. Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/palmetto-bmc.c | 2 ++ hw/ssi/aspeed_smc.c | 60 +++++++++++++++++++++++++++++++++++++++= ++---- include/hw/ssi/aspeed_smc.h | 1 + 3 files changed, 58 insertions(+), 5 deletions(-) diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c index c0bb922f6406..b00757dcbc69 100644 --- a/hw/arm/palmetto-bmc.c +++ b/hw/arm/palmetto-bmc.c @@ -20,6 +20,7 @@ #include "qemu/log.h" #include "sysemu/block-backend.h" #include "sysemu/blockdev.h" +#include "hw/block/flash.h" =20 static struct arm_boot_info palmetto_bmc_binfo =3D { .loader_start =3D AST2400_SDRAM_BASE, @@ -51,6 +52,7 @@ static void palmetto_bmc_init_flashes(AspeedSMCState *s= , const char *flashtype, qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(= dinfo), errp); } + m25p80_set_rom_storage(fl->flash, &fl->mmio); qdev_init_nofail(fl->flash); =20 cs_line =3D qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index cb0b23750bcf..f88edf953dee 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -23,11 +23,13 @@ */ =20 #include "qemu/osdep.h" +#include "qapi/error.h" #include "hw/sysbus.h" #include "sysemu/sysemu.h" #include "qemu/log.h" #include "include/qemu/error-report.h" #include "exec/address-spaces.h" +#include "hw/block/flash.h" =20 #include "hw/ssi/aspeed_smc.h" =20 @@ -198,6 +200,37 @@ static inline bool aspeed_smc_is_writable(const Aspe= edSMCState *s, int cs) return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + cs)); } =20 +/* + * Sanity checks on the command mode and the SPI flash command being + * used + */ +static inline bool aspeed_smc_check_mode(const AspeedSMCState *s, int cs= ) +{ + uint8_t mode =3D aspeed_smc_flash_mode(s, cs); + uint8_t cmd =3D (s->regs[s->r_ctrl0 + cs] >> CTRL_CMD_SHIFT) && CTRL= _CMD_MASK; + bool ret; + + switch (mode) { + case CTRL_READMODE: + ret =3D (cmd =3D=3D 0x3 || cmd =3D=3D 0x0); + break; + case CTRL_FREADMODE: + ret =3D true; + break; + case CTRL_WRITEMODE: + default: + ret =3D false; + break; + } + + if (!ret) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid mode/command: %d/%d\= n", + __func__, cmd, mode); + } + + return ret; +} + static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigne= d size) { AspeedSMCFlash *fl =3D opaque; @@ -210,9 +243,11 @@ static uint64_t aspeed_smc_flash_read(void *opaque, = hwaddr addr, unsigned size) ret |=3D ssi_transfer(s->spi, 0x0) << (8 * i); } } else { - qemu_log_mask(LOG_UNIMP, "%s: usermode not implemented\n", - __func__); - ret =3D -1; + if (aspeed_smc_check_mode(s, fl->id)) { + for (i =3D 0; i < size; i++) { + ret =3D fl->storage[addr + i] << (8 * i); + } + } } =20 return ret; @@ -336,6 +371,12 @@ static void aspeed_smc_write(void *opaque, hwaddr ad= dr, uint64_t data, */ s->regs[addr] =3D value; if (addr >=3D s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) { + int i; + + for (i =3D 0; i < s->num_cs; ++i) { + memory_region_rom_device_set_romd(&s->flashes[i].mmio, + !aspeed_smc_is_usermode(s,= i)); + } aspeed_smc_update_cs(s); } } @@ -355,6 +396,7 @@ static void aspeed_smc_realize(DeviceState *dev, Erro= r **errp) int i; char name[32]; hwaddr offset =3D 0; + Error *err =3D NULL; =20 s->ctrl =3D mc->ctrl; =20 @@ -409,8 +451,16 @@ static void aspeed_smc_realize(DeviceState *dev, Err= or **errp) fl->id =3D i; fl->controller =3D s; fl->size =3D s->ctrl->segments[i].size; - memory_region_init_io(&fl->mmio, OBJECT(s), &aspeed_smc_flash_op= s, - fl, name, fl->size); + memory_region_init_rom_device(&fl->mmio, OBJECT(s), + &aspeed_smc_flash_ops, + fl, name, fl->size, &err); + if (err) { + error_propagate(errp, err); + return; + } + vmstate_register_ram(&fl->mmio, DEVICE(s)); + fl->storage =3D memory_region_get_ram_ptr(&fl->mmio); + memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio); offset +=3D fl->size; } diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index def3b4507e75..4796b4ca0138 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -47,6 +47,7 @@ typedef struct AspeedSMCController { =20 typedef struct AspeedSMCFlash { const struct AspeedSMCState *controller; + uint8_t *storage; =20 uint8_t id; uint32_t size; --=20 2.1.4