From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753542AbcGDRgW (ORCPT ); Mon, 4 Jul 2016 13:36:22 -0400 Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:35467 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753141AbcGDRgV (ORCPT ); Mon, 4 Jul 2016 13:36:21 -0400 Message-ID: <1467653766.2224.76.camel@pengutronix.de> Subject: Re: [PATCH 2/4] dt-bindings: Document the STM32 reset bindings From: Philipp Zabel To: gabriel.fernandez@st.com Cc: Rob Herring , Mark Rutland , Maxime Coquelin , Russell King , patrice.chotard@st.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Date: Mon, 04 Jul 2016 19:36:06 +0200 In-Reply-To: <1467640052-6770-2-git-send-email-gabriel.fernandez@st.com> References: <1467640052-6770-1-git-send-email-gabriel.fernandez@st.com> <1467640052-6770-2-git-send-email-gabriel.fernandez@st.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:100:96de:80ff:fec2:9969 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Montag, den 04.07.2016, 15:47 +0200 schrieb gabriel.fernandez@st.com: > From: Maxime Coquelin > > This adds documentation of device tree bindings for the > STM32 reset controller. > > Signed-off-by: Maxime Coquelin The way I understand Documentation/SubmittingPatches, this should also have your Signed-off-by. > --- > .../devicetree/bindings/reset/st,stm32-rcc.txt | 50 ++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/st,stm32-rcc.txt > > diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt > new file mode 100644 > index 0000000..333080c > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt > @@ -0,0 +1,50 @@ > +STMicroelectronics STM32 Peripheral Reset Controller > +==================================================== > + > +The RCC IP is both a reset and a clock controller. This documentation only > +documents the reset part. > + > +Please also refer to reset.txt in this directory for common reset > +controller binding usage. > + > +Required properties: > +- compatible: Should be "st,stm32-rcc" > +- reg: should be register base and length as documented in the > + datasheet > +- #reset-cells: 1, see below > + > +example: > + > +rcc: reset@40023800 { > + #reset-cells = <1>; > + compatible = "st,stm32-rcc"; > + reg = <0x40023800 0x400>; > +}; > + > +Specifying softreset control of devices > +======================================= > + > +Device nodes should specify the reset channel required in their "resets" > +property, containing a phandle to the reset device node and an index specifying > +which channel to use. > +The index is the bit number within the RCC registers bank, starting from RCC > +base address. > +It is calculated as: index = register_offset / 4 * 32 + bit_offset. > +Where bit_offset is the bit offset within the register. > +For example, for CRC reset: > + crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 I see you decided to keep the register offset encoded in the reset index. > + > +To simplify the usagen and to share bit definition with the clock driver of s/usagen/usage/ > +the RCC IP, macros are available to generate the index in human-readble > +format. > + > +For STM32F4 series, the macro are available here: > + - include/dt-bindings/mfd/stm32f4-rcc.h If DT and ARM/STI and maintainers agree with the binding and header macros, I'm inclined to take patches 1-3. regards Philipp From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philipp Zabel Subject: Re: [PATCH 2/4] dt-bindings: Document the STM32 reset bindings Date: Mon, 04 Jul 2016 19:36:06 +0200 Message-ID: <1467653766.2224.76.camel@pengutronix.de> References: <1467640052-6770-1-git-send-email-gabriel.fernandez@st.com> <1467640052-6770-2-git-send-email-gabriel.fernandez@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1467640052-6770-2-git-send-email-gabriel.fernandez-qxv4g6HH51o@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: gabriel.fernandez-qxv4g6HH51o@public.gmane.org Cc: Rob Herring , Mark Rutland , Maxime Coquelin , Russell King , patrice.chotard-qxv4g6HH51o@public.gmane.org, alexandre.torgue-qxv4g6HH51o@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org Am Montag, den 04.07.2016, 15:47 +0200 schrieb gabriel.fernandez-qxv4g6HH51o@public.gmane.org: > From: Maxime Coquelin > > This adds documentation of device tree bindings for the > STM32 reset controller. > > Signed-off-by: Maxime Coquelin The way I understand Documentation/SubmittingPatches, this should also have your Signed-off-by. > --- > .../devicetree/bindings/reset/st,stm32-rcc.txt | 50 ++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/st,stm32-rcc.txt > > diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt > new file mode 100644 > index 0000000..333080c > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt > @@ -0,0 +1,50 @@ > +STMicroelectronics STM32 Peripheral Reset Controller > +==================================================== > + > +The RCC IP is both a reset and a clock controller. This documentation only > +documents the reset part. > + > +Please also refer to reset.txt in this directory for common reset > +controller binding usage. > + > +Required properties: > +- compatible: Should be "st,stm32-rcc" > +- reg: should be register base and length as documented in the > + datasheet > +- #reset-cells: 1, see below > + > +example: > + > +rcc: reset@40023800 { > + #reset-cells = <1>; > + compatible = "st,stm32-rcc"; > + reg = <0x40023800 0x400>; > +}; > + > +Specifying softreset control of devices > +======================================= > + > +Device nodes should specify the reset channel required in their "resets" > +property, containing a phandle to the reset device node and an index specifying > +which channel to use. > +The index is the bit number within the RCC registers bank, starting from RCC > +base address. > +It is calculated as: index = register_offset / 4 * 32 + bit_offset. > +Where bit_offset is the bit offset within the register. > +For example, for CRC reset: > + crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 I see you decided to keep the register offset encoded in the reset index. > + > +To simplify the usagen and to share bit definition with the clock driver of s/usagen/usage/ > +the RCC IP, macros are available to generate the index in human-readble > +format. > + > +For STM32F4 series, the macro are available here: > + - include/dt-bindings/mfd/stm32f4-rcc.h If DT and ARM/STI and maintainers agree with the binding and header macros, I'm inclined to take patches 1-3. regards Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: p.zabel@pengutronix.de (Philipp Zabel) Date: Mon, 04 Jul 2016 19:36:06 +0200 Subject: [PATCH 2/4] dt-bindings: Document the STM32 reset bindings In-Reply-To: <1467640052-6770-2-git-send-email-gabriel.fernandez@st.com> References: <1467640052-6770-1-git-send-email-gabriel.fernandez@st.com> <1467640052-6770-2-git-send-email-gabriel.fernandez@st.com> Message-ID: <1467653766.2224.76.camel@pengutronix.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Am Montag, den 04.07.2016, 15:47 +0200 schrieb gabriel.fernandez at st.com: > From: Maxime Coquelin > > This adds documentation of device tree bindings for the > STM32 reset controller. > > Signed-off-by: Maxime Coquelin The way I understand Documentation/SubmittingPatches, this should also have your Signed-off-by. > --- > .../devicetree/bindings/reset/st,stm32-rcc.txt | 50 ++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/st,stm32-rcc.txt > > diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt > new file mode 100644 > index 0000000..333080c > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt > @@ -0,0 +1,50 @@ > +STMicroelectronics STM32 Peripheral Reset Controller > +==================================================== > + > +The RCC IP is both a reset and a clock controller. This documentation only > +documents the reset part. > + > +Please also refer to reset.txt in this directory for common reset > +controller binding usage. > + > +Required properties: > +- compatible: Should be "st,stm32-rcc" > +- reg: should be register base and length as documented in the > + datasheet > +- #reset-cells: 1, see below > + > +example: > + > +rcc: reset at 40023800 { > + #reset-cells = <1>; > + compatible = "st,stm32-rcc"; > + reg = <0x40023800 0x400>; > +}; > + > +Specifying softreset control of devices > +======================================= > + > +Device nodes should specify the reset channel required in their "resets" > +property, containing a phandle to the reset device node and an index specifying > +which channel to use. > +The index is the bit number within the RCC registers bank, starting from RCC > +base address. > +It is calculated as: index = register_offset / 4 * 32 + bit_offset. > +Where bit_offset is the bit offset within the register. > +For example, for CRC reset: > + crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 I see you decided to keep the register offset encoded in the reset index. > + > +To simplify the usagen and to share bit definition with the clock driver of s/usagen/usage/ > +the RCC IP, macros are available to generate the index in human-readble > +format. > + > +For STM32F4 series, the macro are available here: > + - include/dt-bindings/mfd/stm32f4-rcc.h If DT and ARM/STI and maintainers agree with the binding and header macros, I'm inclined to take patches 1-3. regards Philipp