From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932769AbcGEBOs (ORCPT ); Mon, 4 Jul 2016 21:14:48 -0400 Received: from anholt.net ([50.246.234.109]:43962 "EHLO anholt.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932700AbcGEBOo (ORCPT ); Mon, 4 Jul 2016 21:14:44 -0400 From: Eric Anholt To: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org, Eric Anholt Subject: [PATCH 3/7] drm/vc4: Add a bitmap of branch targets during shader validation. Date: Mon, 4 Jul 2016 18:14:36 -0700 Message-Id: <1467681280-20317-4-git-send-email-eric@anholt.net> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1467681280-20317-1-git-send-email-eric@anholt.net> References: <1467681280-20317-1-git-send-email-eric@anholt.net> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This isn't used yet, it's just a first step toward loop validation. During the main parsing of instructions, we need to know when we hit a new basic block so that we can reset validated state. Signed-off-by: Eric Anholt --- drivers/gpu/drm/vc4/vc4_qpu_defines.h | 12 +++ drivers/gpu/drm/vc4/vc4_validate_shaders.c | 114 ++++++++++++++++++++++++++++- 2 files changed, 124 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_qpu_defines.h b/drivers/gpu/drm/vc4/vc4_qpu_defines.h index d5c2f3c85ebb..82ef0e525d55 100644 --- a/drivers/gpu/drm/vc4/vc4_qpu_defines.h +++ b/drivers/gpu/drm/vc4/vc4_qpu_defines.h @@ -230,6 +230,15 @@ enum qpu_unpack_r4 { #define QPU_COND_MUL_SHIFT 46 #define QPU_COND_MUL_MASK QPU_MASK(48, 46) +#define QPU_BRANCH_COND_SHIFT 52 +#define QPU_BRANCH_COND_MASK QPU_MASK(55, 52) + +#define QPU_BRANCH_REL ((uint64_t)1 << 51) +#define QPU_BRANCH_REG ((uint64_t)1 << 50) + +#define QPU_BRANCH_RADDR_A_SHIFT 45 +#define QPU_BRANCH_RADDR_A_MASK QPU_MASK(49, 45) + #define QPU_SF ((uint64_t)1 << 45) #define QPU_WADDR_ADD_SHIFT 38 @@ -261,4 +270,7 @@ enum qpu_unpack_r4 { #define QPU_OP_ADD_SHIFT 24 #define QPU_OP_ADD_MASK QPU_MASK(28, 24) +#define QPU_BRANCH_TARGET_SHIFT 0 +#define QPU_BRANCH_TARGET_MASK QPU_MASK(31, 0) + #endif /* VC4_QPU_DEFINES_H */ diff --git a/drivers/gpu/drm/vc4/vc4_validate_shaders.c b/drivers/gpu/drm/vc4/vc4_validate_shaders.c index 771d904653f2..bcf3c31b2765 100644 --- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c +++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c @@ -59,6 +59,13 @@ struct vc4_shader_validation_state { */ uint32_t live_min_clamp_offsets[32 + 32 + 4]; bool live_max_clamp_regs[32 + 32 + 4]; + + /* Bitfield of which IPs are used as branch targets. + * + * Used for validation that the uniform stream is updated at the right + * points and clearing the texturing/clamping state. + */ + unsigned long *branch_targets; }; static uint32_t @@ -418,13 +425,104 @@ check_instruction_reads(uint64_t inst, return true; } +/* Make sure that all branches are absolute and point within the shader, and + * note their targets for later. + */ +static bool +vc4_validate_branches(struct vc4_shader_validation_state *validation_state) +{ + uint32_t max_branch_target = 0; + bool found_shader_end = false; + int ip; + int shader_end_ip = 0; + int last_branch = -2; + + for (ip = 0; ip < validation_state->max_ip; ip++) { + uint64_t inst = validation_state->shader[ip]; + int32_t branch_imm = QPU_GET_FIELD(inst, QPU_BRANCH_TARGET); + uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); + uint32_t after_delay_ip = ip + 4; + uint32_t branch_target_ip; + + if (sig == QPU_SIG_PROG_END) { + shader_end_ip = ip; + found_shader_end = true; + continue; + } + + if (sig != QPU_SIG_BRANCH) + continue; + + if (ip - last_branch < 4) { + DRM_ERROR("Branch at %d during delay slots\n", ip); + return false; + } + last_branch = ip; + + if (inst & QPU_BRANCH_REG) { + DRM_ERROR("branching from register relative " + "not supported\n"); + return false; + } + + if (!(inst & QPU_BRANCH_REL)) { + DRM_ERROR("relative branching required\n"); + return false; + } + + /* The actual branch target is the instruction after the delay + * slots, plus whatever byte offset is in the low 32 bits of + * the instruction. Make sure we're not branching beyond the + * end of the shader object. + */ + if (branch_imm % sizeof(inst) != 0) { + DRM_ERROR("branch target not aligned\n"); + return false; + }; + + branch_target_ip = after_delay_ip + (branch_imm >> 3); + if (branch_target_ip >= validation_state->max_ip) { + DRM_ERROR("Branch at %d outside of shader (ip %d/%d)\n", + ip, branch_target_ip, + validation_state->max_ip); + return false; + } + set_bit(branch_target_ip, validation_state->branch_targets); + + /* Make sure that the non-branching path is also not outside + * the shader. + */ + if (after_delay_ip >= validation_state->max_ip) { + DRM_ERROR("Branch at %d continues past shader end " + "(%d/%d)\n", + ip, after_delay_ip, validation_state->max_ip); + return false; + } + set_bit(after_delay_ip, validation_state->branch_targets); + max_branch_target = max(max_branch_target, after_delay_ip); + + /* There are two delay slots after program end is signaled + * that are still executed, then we're finished. + */ + if (found_shader_end && ip == shader_end_ip + 2) + break; + } + + if (max_branch_target > shader_end_ip) { + DRM_ERROR("Branch landed after QPU_SIG_PROG_END"); + return false; + } + + return true; +} + struct vc4_validated_shader_info * vc4_validate_shader(struct drm_gem_cma_object *shader_obj) { bool found_shader_end = false; int shader_end_ip = 0; uint32_t ip; - struct vc4_validated_shader_info *validated_shader; + struct vc4_validated_shader_info *validated_shader = NULL; struct vc4_shader_validation_state validation_state; int i; @@ -437,9 +535,18 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) for (i = 0; i < ARRAY_SIZE(validation_state.live_min_clamp_offsets); i++) validation_state.live_min_clamp_offsets[i] = ~0; + validation_state.branch_targets = + kcalloc(BITS_TO_LONGS(validation_state.max_ip), + sizeof(unsigned long), GFP_KERNEL); + if (!validation_state.branch_targets) + goto fail; + validated_shader = kcalloc(1, sizeof(*validated_shader), GFP_KERNEL); if (!validated_shader) - return NULL; + goto fail; + + if (!vc4_validate_branches(&validation_state)) + goto fail; for (ip = 0; ip < validation_state.max_ip; ip++) { uint64_t inst = validation_state.shader[ip]; @@ -508,9 +615,12 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) (validated_shader->uniforms_size + 4 * validated_shader->num_texture_samples); + kfree(validation_state.branch_targets); + return validated_shader; fail: + kfree(validation_state.branch_targets); if (validated_shader) { kfree(validated_shader->texture_samples); kfree(validated_shader); -- 2.8.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Anholt Subject: [PATCH 3/7] drm/vc4: Add a bitmap of branch targets during shader validation. Date: Mon, 4 Jul 2016 18:14:36 -0700 Message-ID: <1467681280-20317-4-git-send-email-eric@anholt.net> References: <1467681280-20317-1-git-send-email-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from anholt.net (anholt.net [50.246.234.109]) by gabe.freedesktop.org (Postfix) with ESMTP id 38D176E556 for ; Tue, 5 Jul 2016 01:14:44 +0000 (UTC) In-Reply-To: <1467681280-20317-1-git-send-email-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org List-Id: dri-devel@lists.freedesktop.org VGhpcyBpc24ndCB1c2VkIHlldCwgaXQncyBqdXN0IGEgZmlyc3Qgc3RlcCB0b3dhcmQgbG9vcCB2 YWxpZGF0aW9uLgpEdXJpbmcgdGhlIG1haW4gcGFyc2luZyBvZiBpbnN0cnVjdGlvbnMsIHdlIG5l ZWQgdG8ga25vdyB3aGVuIHdlIGhpdCBhCm5ldyBiYXNpYyBibG9jayBzbyB0aGF0IHdlIGNhbiBy ZXNldCB2YWxpZGF0ZWQgc3RhdGUuCgpTaWduZWQtb2ZmLWJ5OiBFcmljIEFuaG9sdCA8ZXJpY0Bh bmhvbHQubmV0PgotLS0KIGRyaXZlcnMvZ3B1L2RybS92YzQvdmM0X3FwdV9kZWZpbmVzLmggICAg ICB8ICAxMiArKysKIGRyaXZlcnMvZ3B1L2RybS92YzQvdmM0X3ZhbGlkYXRlX3NoYWRlcnMuYyB8 IDExNCArKysrKysrKysrKysrKysrKysrKysrKysrKysrLQogMiBmaWxlcyBjaGFuZ2VkLCAxMjQg aW5zZXJ0aW9ucygrKSwgMiBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9k cm0vdmM0L3ZjNF9xcHVfZGVmaW5lcy5oIGIvZHJpdmVycy9ncHUvZHJtL3ZjNC92YzRfcXB1X2Rl ZmluZXMuaAppbmRleCBkNWMyZjNjODVlYmIuLjgyZWYwZTUyNWQ1NSAxMDA2NDQKLS0tIGEvZHJp dmVycy9ncHUvZHJtL3ZjNC92YzRfcXB1X2RlZmluZXMuaAorKysgYi9kcml2ZXJzL2dwdS9kcm0v dmM0L3ZjNF9xcHVfZGVmaW5lcy5oCkBAIC0yMzAsNiArMjMwLDE1IEBAIGVudW0gcXB1X3VucGFj a19yNCB7CiAjZGVmaW5lIFFQVV9DT05EX01VTF9TSElGVCAgICAgICAgICAgICAgNDYKICNkZWZp bmUgUVBVX0NPTkRfTVVMX01BU0sgICAgICAgICAgICAgICBRUFVfTUFTSyg0OCwgNDYpCiAKKyNk ZWZpbmUgUVBVX0JSQU5DSF9DT05EX1NISUZUICAgICAgICAgICA1MgorI2RlZmluZSBRUFVfQlJB TkNIX0NPTkRfTUFTSyAgICAgICAgICAgIFFQVV9NQVNLKDU1LCA1MikKKworI2RlZmluZSBRUFVf QlJBTkNIX1JFTCAgICAgICAgICAgICAgICAgICgodWludDY0X3QpMSA8PCA1MSkKKyNkZWZpbmUg UVBVX0JSQU5DSF9SRUcgICAgICAgICAgICAgICAgICAoKHVpbnQ2NF90KTEgPDwgNTApCisKKyNk ZWZpbmUgUVBVX0JSQU5DSF9SQUREUl9BX1NISUZUICAgICAgICA0NQorI2RlZmluZSBRUFVfQlJB TkNIX1JBRERSX0FfTUFTSyAgICAgICAgIFFQVV9NQVNLKDQ5LCA0NSkKKwogI2RlZmluZSBRUFVf U0YgICAgICAgICAgICAgICAgICAgICAgICAgICgodWludDY0X3QpMSA8PCA0NSkKIAogI2RlZmlu ZSBRUFVfV0FERFJfQUREX1NISUZUICAgICAgICAgICAgIDM4CkBAIC0yNjEsNCArMjcwLDcgQEAg ZW51bSBxcHVfdW5wYWNrX3I0IHsKICNkZWZpbmUgUVBVX09QX0FERF9TSElGVCAgICAgICAgICAg ICAgICAyNAogI2RlZmluZSBRUFVfT1BfQUREX01BU0sgICAgICAgICAgICAgICAgIFFQVV9NQVNL KDI4LCAyNCkKIAorI2RlZmluZSBRUFVfQlJBTkNIX1RBUkdFVF9TSElGVCAgICAgICAgIDAKKyNk ZWZpbmUgUVBVX0JSQU5DSF9UQVJHRVRfTUFTSyAgICAgICAgICBRUFVfTUFTSygzMSwgMCkKKwog I2VuZGlmIC8qIFZDNF9RUFVfREVGSU5FU19IICovCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9k cm0vdmM0L3ZjNF92YWxpZGF0ZV9zaGFkZXJzLmMgYi9kcml2ZXJzL2dwdS9kcm0vdmM0L3ZjNF92 YWxpZGF0ZV9zaGFkZXJzLmMKaW5kZXggNzcxZDkwNDY1M2YyLi5iY2YzYzMxYjI3NjUgMTAwNjQ0 Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS92YzQvdmM0X3ZhbGlkYXRlX3NoYWRlcnMuYworKysgYi9k cml2ZXJzL2dwdS9kcm0vdmM0L3ZjNF92YWxpZGF0ZV9zaGFkZXJzLmMKQEAgLTU5LDYgKzU5LDEz IEBAIHN0cnVjdCB2YzRfc2hhZGVyX3ZhbGlkYXRpb25fc3RhdGUgewogCSAqLwogCXVpbnQzMl90 IGxpdmVfbWluX2NsYW1wX29mZnNldHNbMzIgKyAzMiArIDRdOwogCWJvb2wgbGl2ZV9tYXhfY2xh bXBfcmVnc1szMiArIDMyICsgNF07CisKKwkvKiBCaXRmaWVsZCBvZiB3aGljaCBJUHMgYXJlIHVz ZWQgYXMgYnJhbmNoIHRhcmdldHMuCisJICoKKwkgKiBVc2VkIGZvciB2YWxpZGF0aW9uIHRoYXQg dGhlIHVuaWZvcm0gc3RyZWFtIGlzIHVwZGF0ZWQgYXQgdGhlIHJpZ2h0CisJICogcG9pbnRzIGFu ZCBjbGVhcmluZyB0aGUgdGV4dHVyaW5nL2NsYW1waW5nIHN0YXRlLgorCSAqLworCXVuc2lnbmVk IGxvbmcgKmJyYW5jaF90YXJnZXRzOwogfTsKIAogc3RhdGljIHVpbnQzMl90CkBAIC00MTgsMTMg KzQyNSwxMDQgQEAgY2hlY2tfaW5zdHJ1Y3Rpb25fcmVhZHModWludDY0X3QgaW5zdCwKIAlyZXR1 cm4gdHJ1ZTsKIH0KIAorLyogTWFrZSBzdXJlIHRoYXQgYWxsIGJyYW5jaGVzIGFyZSBhYnNvbHV0 ZSBhbmQgcG9pbnQgd2l0aGluIHRoZSBzaGFkZXIsIGFuZAorICogbm90ZSB0aGVpciB0YXJnZXRz IGZvciBsYXRlci4KKyAqLworc3RhdGljIGJvb2wKK3ZjNF92YWxpZGF0ZV9icmFuY2hlcyhzdHJ1 Y3QgdmM0X3NoYWRlcl92YWxpZGF0aW9uX3N0YXRlICp2YWxpZGF0aW9uX3N0YXRlKQoreworCXVp bnQzMl90IG1heF9icmFuY2hfdGFyZ2V0ID0gMDsKKwlib29sIGZvdW5kX3NoYWRlcl9lbmQgPSBm YWxzZTsKKwlpbnQgaXA7CisJaW50IHNoYWRlcl9lbmRfaXAgPSAwOworCWludCBsYXN0X2JyYW5j aCA9IC0yOworCisJZm9yIChpcCA9IDA7IGlwIDwgdmFsaWRhdGlvbl9zdGF0ZS0+bWF4X2lwOyBp cCsrKSB7CisJCXVpbnQ2NF90IGluc3QgPSB2YWxpZGF0aW9uX3N0YXRlLT5zaGFkZXJbaXBdOwor CQlpbnQzMl90IGJyYW5jaF9pbW0gPSBRUFVfR0VUX0ZJRUxEKGluc3QsIFFQVV9CUkFOQ0hfVEFS R0VUKTsKKwkJdWludDMyX3Qgc2lnID0gUVBVX0dFVF9GSUVMRChpbnN0LCBRUFVfU0lHKTsKKwkJ dWludDMyX3QgYWZ0ZXJfZGVsYXlfaXAgPSBpcCArIDQ7CisJCXVpbnQzMl90IGJyYW5jaF90YXJn ZXRfaXA7CisKKwkJaWYgKHNpZyA9PSBRUFVfU0lHX1BST0dfRU5EKSB7CisJCQlzaGFkZXJfZW5k X2lwID0gaXA7CisJCQlmb3VuZF9zaGFkZXJfZW5kID0gdHJ1ZTsKKwkJCWNvbnRpbnVlOworCQl9 CisKKwkJaWYgKHNpZyAhPSBRUFVfU0lHX0JSQU5DSCkKKwkJCWNvbnRpbnVlOworCisJCWlmIChp cCAtIGxhc3RfYnJhbmNoIDwgNCkgeworCQkJRFJNX0VSUk9SKCJCcmFuY2ggYXQgJWQgZHVyaW5n IGRlbGF5IHNsb3RzXG4iLCBpcCk7CisJCQlyZXR1cm4gZmFsc2U7CisJCX0KKwkJbGFzdF9icmFu Y2ggPSBpcDsKKworCQlpZiAoaW5zdCAmIFFQVV9CUkFOQ0hfUkVHKSB7CisJCQlEUk1fRVJST1Io ImJyYW5jaGluZyBmcm9tIHJlZ2lzdGVyIHJlbGF0aXZlICIKKwkJCQkgICJub3Qgc3VwcG9ydGVk XG4iKTsKKwkJCXJldHVybiBmYWxzZTsKKwkJfQorCisJCWlmICghKGluc3QgJiBRUFVfQlJBTkNI X1JFTCkpIHsKKwkJCURSTV9FUlJPUigicmVsYXRpdmUgYnJhbmNoaW5nIHJlcXVpcmVkXG4iKTsK KwkJCXJldHVybiBmYWxzZTsKKwkJfQorCisJCS8qIFRoZSBhY3R1YWwgYnJhbmNoIHRhcmdldCBp cyB0aGUgaW5zdHJ1Y3Rpb24gYWZ0ZXIgdGhlIGRlbGF5CisJCSAqIHNsb3RzLCBwbHVzIHdoYXRl dmVyIGJ5dGUgb2Zmc2V0IGlzIGluIHRoZSBsb3cgMzIgYml0cyBvZgorCQkgKiB0aGUgaW5zdHJ1 Y3Rpb24uICBNYWtlIHN1cmUgd2UncmUgbm90IGJyYW5jaGluZyBiZXlvbmQgdGhlCisJCSAqIGVu ZCBvZiB0aGUgc2hhZGVyIG9iamVjdC4KKwkJICovCisJCWlmIChicmFuY2hfaW1tICUgc2l6ZW9m KGluc3QpICE9IDApIHsKKwkJCURSTV9FUlJPUigiYnJhbmNoIHRhcmdldCBub3QgYWxpZ25lZFxu Iik7CisJCQlyZXR1cm4gZmFsc2U7CisJCX07CisKKwkJYnJhbmNoX3RhcmdldF9pcCA9IGFmdGVy X2RlbGF5X2lwICsgKGJyYW5jaF9pbW0gPj4gMyk7CisJCWlmIChicmFuY2hfdGFyZ2V0X2lwID49 IHZhbGlkYXRpb25fc3RhdGUtPm1heF9pcCkgeworCQkJRFJNX0VSUk9SKCJCcmFuY2ggYXQgJWQg b3V0c2lkZSBvZiBzaGFkZXIgKGlwICVkLyVkKVxuIiwKKwkJCQkgIGlwLCBicmFuY2hfdGFyZ2V0 X2lwLAorCQkJCSAgdmFsaWRhdGlvbl9zdGF0ZS0+bWF4X2lwKTsKKwkJCXJldHVybiBmYWxzZTsK KwkJfQorCQlzZXRfYml0KGJyYW5jaF90YXJnZXRfaXAsIHZhbGlkYXRpb25fc3RhdGUtPmJyYW5j aF90YXJnZXRzKTsKKworCQkvKiBNYWtlIHN1cmUgdGhhdCB0aGUgbm9uLWJyYW5jaGluZyBwYXRo IGlzIGFsc28gbm90IG91dHNpZGUKKwkJICogdGhlIHNoYWRlci4KKwkJICovCisJCWlmIChhZnRl cl9kZWxheV9pcCA+PSB2YWxpZGF0aW9uX3N0YXRlLT5tYXhfaXApIHsKKwkJCURSTV9FUlJPUigi QnJhbmNoIGF0ICVkIGNvbnRpbnVlcyBwYXN0IHNoYWRlciBlbmQgIgorCQkJCSAgIiglZC8lZClc biIsCisJCQkJICBpcCwgYWZ0ZXJfZGVsYXlfaXAsIHZhbGlkYXRpb25fc3RhdGUtPm1heF9pcCk7 CisJCQlyZXR1cm4gZmFsc2U7CisJCX0KKwkJc2V0X2JpdChhZnRlcl9kZWxheV9pcCwgdmFsaWRh dGlvbl9zdGF0ZS0+YnJhbmNoX3RhcmdldHMpOworCQltYXhfYnJhbmNoX3RhcmdldCA9IG1heCht YXhfYnJhbmNoX3RhcmdldCwgYWZ0ZXJfZGVsYXlfaXApOworCisJCS8qIFRoZXJlIGFyZSB0d28g ZGVsYXkgc2xvdHMgYWZ0ZXIgcHJvZ3JhbSBlbmQgaXMgc2lnbmFsZWQKKwkJICogdGhhdCBhcmUg c3RpbGwgZXhlY3V0ZWQsIHRoZW4gd2UncmUgZmluaXNoZWQuCisJCSAqLworCQlpZiAoZm91bmRf c2hhZGVyX2VuZCAmJiBpcCA9PSBzaGFkZXJfZW5kX2lwICsgMikKKwkJCWJyZWFrOworCX0KKwor CWlmIChtYXhfYnJhbmNoX3RhcmdldCA+IHNoYWRlcl9lbmRfaXApIHsKKwkJRFJNX0VSUk9SKCJC cmFuY2ggbGFuZGVkIGFmdGVyIFFQVV9TSUdfUFJPR19FTkQiKTsKKwkJcmV0dXJuIGZhbHNlOwor CX0KKworCXJldHVybiB0cnVlOworfQorCiBzdHJ1Y3QgdmM0X3ZhbGlkYXRlZF9zaGFkZXJfaW5m byAqCiB2YzRfdmFsaWRhdGVfc2hhZGVyKHN0cnVjdCBkcm1fZ2VtX2NtYV9vYmplY3QgKnNoYWRl cl9vYmopCiB7CiAJYm9vbCBmb3VuZF9zaGFkZXJfZW5kID0gZmFsc2U7CiAJaW50IHNoYWRlcl9l bmRfaXAgPSAwOwogCXVpbnQzMl90IGlwOwotCXN0cnVjdCB2YzRfdmFsaWRhdGVkX3NoYWRlcl9p bmZvICp2YWxpZGF0ZWRfc2hhZGVyOworCXN0cnVjdCB2YzRfdmFsaWRhdGVkX3NoYWRlcl9pbmZv ICp2YWxpZGF0ZWRfc2hhZGVyID0gTlVMTDsKIAlzdHJ1Y3QgdmM0X3NoYWRlcl92YWxpZGF0aW9u X3N0YXRlIHZhbGlkYXRpb25fc3RhdGU7CiAJaW50IGk7CiAKQEAgLTQzNyw5ICs1MzUsMTggQEAg dmM0X3ZhbGlkYXRlX3NoYWRlcihzdHJ1Y3QgZHJtX2dlbV9jbWFfb2JqZWN0ICpzaGFkZXJfb2Jq KQogCWZvciAoaSA9IDA7IGkgPCBBUlJBWV9TSVpFKHZhbGlkYXRpb25fc3RhdGUubGl2ZV9taW5f Y2xhbXBfb2Zmc2V0cyk7IGkrKykKIAkJdmFsaWRhdGlvbl9zdGF0ZS5saXZlX21pbl9jbGFtcF9v ZmZzZXRzW2ldID0gfjA7CiAKKwl2YWxpZGF0aW9uX3N0YXRlLmJyYW5jaF90YXJnZXRzID0KKwkJ a2NhbGxvYyhCSVRTX1RPX0xPTkdTKHZhbGlkYXRpb25fc3RhdGUubWF4X2lwKSwKKwkJCXNpemVv Zih1bnNpZ25lZCBsb25nKSwgR0ZQX0tFUk5FTCk7CisJaWYgKCF2YWxpZGF0aW9uX3N0YXRlLmJy YW5jaF90YXJnZXRzKQorCQlnb3RvIGZhaWw7CisKIAl2YWxpZGF0ZWRfc2hhZGVyID0ga2NhbGxv YygxLCBzaXplb2YoKnZhbGlkYXRlZF9zaGFkZXIpLCBHRlBfS0VSTkVMKTsKIAlpZiAoIXZhbGlk YXRlZF9zaGFkZXIpCi0JCXJldHVybiBOVUxMOworCQlnb3RvIGZhaWw7CisKKwlpZiAoIXZjNF92 YWxpZGF0ZV9icmFuY2hlcygmdmFsaWRhdGlvbl9zdGF0ZSkpCisJCWdvdG8gZmFpbDsKIAogCWZv ciAoaXAgPSAwOyBpcCA8IHZhbGlkYXRpb25fc3RhdGUubWF4X2lwOyBpcCsrKSB7CiAJCXVpbnQ2 NF90IGluc3QgPSB2YWxpZGF0aW9uX3N0YXRlLnNoYWRlcltpcF07CkBAIC01MDgsOSArNjE1LDEy IEBAIHZjNF92YWxpZGF0ZV9zaGFkZXIoc3RydWN0IGRybV9nZW1fY21hX29iamVjdCAqc2hhZGVy X29iaikKIAkJKHZhbGlkYXRlZF9zaGFkZXItPnVuaWZvcm1zX3NpemUgKwogCQkgNCAqIHZhbGlk YXRlZF9zaGFkZXItPm51bV90ZXh0dXJlX3NhbXBsZXMpOwogCisJa2ZyZWUodmFsaWRhdGlvbl9z dGF0ZS5icmFuY2hfdGFyZ2V0cyk7CisKIAlyZXR1cm4gdmFsaWRhdGVkX3NoYWRlcjsKIAogZmFp bDoKKwlrZnJlZSh2YWxpZGF0aW9uX3N0YXRlLmJyYW5jaF90YXJnZXRzKTsKIAlpZiAodmFsaWRh dGVkX3NoYWRlcikgewogCQlrZnJlZSh2YWxpZGF0ZWRfc2hhZGVyLT50ZXh0dXJlX3NhbXBsZXMp OwogCQlrZnJlZSh2YWxpZGF0ZWRfc2hhZGVyKTsKLS0gCjIuOC4xCgpfX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRy aS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5v cmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK