From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34279) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLiNy-0008Vv-9R for qemu-devel@nongnu.org; Fri, 08 Jul 2016 22:52:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bLiNt-0001KF-AH for qemu-devel@nongnu.org; Fri, 08 Jul 2016 22:52:53 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:52545 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLiNt-0001KB-5H for qemu-devel@nongnu.org; Fri, 08 Jul 2016 22:52:49 -0400 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u692nKQF001037 for ; Fri, 8 Jul 2016 22:52:48 -0400 Received: from e23smtp05.au.ibm.com (e23smtp05.au.ibm.com [202.81.31.147]) by mx0a-001b2d01.pphosted.com with ESMTP id 2415xp8vk5-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 08 Jul 2016 22:52:47 -0400 Received: from localhost by e23smtp05.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sat, 9 Jul 2016 12:52:45 +1000 From: Benjamin Herrenschmidt Reply-To: benh@au1.ibm.com Date: Sat, 09 Jul 2016 12:52:37 +1000 In-Reply-To: <1468032411.20552.21.camel@kernel.crashing.org> References: <1467355319-28406-1-git-send-email-david@gibson.dropbear.id.au> <1467355319-28406-6-git-send-email-david@gibson.dropbear.id.au> <1468032411.20552.21.camel@kernel.crashing.org> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Message-Id: <1468032757.20552.22.camel@au1.ibm.com> Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [Qemu-ppc] [PULL 05/23] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Cave-Ayland , David Gibson , peter.maydell@linaro.org Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, =?ISO-8859-1?Q?C=E9dric?= Le Goater On Sat, 2016-07-09 at 12:46 +1000, Benjamin Herrenschmidt wrote: > On Sat, 2016-07-09 at 01:43 +0100, Mark Cave-Ayland wrote: > > On 01/07/16 07:41, David Gibson wrote: > >=20 > > > From: Benjamin Herrenschmidt=C2=A0 > > >=20 > > > The architecture specifies that any instruction that sets MSR:PR > > > will also > > > set MSR:EE, IR and DR. >=20 > =C2=A0.../... >=20 > > Unfortunately this patch causes a regression and breaks booting OS > > 9 and > > OS X under qemu-system-ppc. >=20 > Any idea what is breaking specifically ? The architecture is pretty > clear > here, could it be that they rely on old implementations allowing the > incorrect combination ? >=20 > Maybe we can make the restriction 64-bit server only... Additionally,=C2=A0hreg_compute_mem_idx() will treat PR=3D1 as DR=3D1/IR=3D= 1 as well ! That means that if those old processors allow PR=3D1 and IR or DR=3D0 and MacOS uses it, we do have a TLB coherency problem in qemu. Cheers, Ben.