From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752572AbcGUMkt (ORCPT ); Thu, 21 Jul 2016 08:40:49 -0400 Received: from mail-lf0-f50.google.com ([209.85.215.50]:34795 "EHLO mail-lf0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752535AbcGUMkp (ORCPT ); Thu, 21 Jul 2016 08:40:45 -0400 From: Grzegorz Jaszczyk To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: robh+dt@kernel.org, mark.rutland@arm.com, jason@lakedaemon.net, andrew@lunn.ch, sebastian.hesselbarth@gmail.com, linux@armlinux.org.uk, thomas.petazzoni@free-electrons.com, gregory.clement@free-electrons.com, mw@semihalf.com, jaz@semihalf.com, alior@marvell.com Subject: [PATCH 07/18] ARM: mvebu: a39x: update the SDHCI node on Armada 39x Date: Thu, 21 Jul 2016 14:44:03 +0200 Message-Id: <1469105055-25181-8-git-send-email-jaz@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1469105055-25181-1-git-send-email-jaz@semihalf.com> References: <1469105055-25181-1-git-send-email-jaz@semihalf.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit 1140011ee9d9 ("mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes") has extended the Device Tree binding used to describe PXAv3 SDHCI controllers in order to be able to use the SDR50 and DDR50 modes. This commit updates the Device Tree description of the Armada 39x SDHCI controller in other to take advantage of this functionality. Signed-off-by: Grzegorz Jaszczyk --- arch/arm/boot/dts/armada-39x.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index dc6efd3..cb66f20 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -380,7 +380,10 @@ sdhci@d8000 { compatible = "marvell,armada-380-sdhci"; - reg = <0xd8000 0x1000>, <0xdc000 0x100>; + reg-names = "sdhci", "mbus", "conf-sdio3"; + reg = <0xd8000 0x1000>, + <0xdc000 0x100>, + <0x18454 0x4>; interrupts = ; clocks = <&gateclk 17>; mrvl,clk-delay-cycles = <0x1F>; -- 1.8.3.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: jaz@semihalf.com (Grzegorz Jaszczyk) Date: Thu, 21 Jul 2016 14:44:03 +0200 Subject: [PATCH 07/18] ARM: mvebu: a39x: update the SDHCI node on Armada 39x In-Reply-To: <1469105055-25181-1-git-send-email-jaz@semihalf.com> References: <1469105055-25181-1-git-send-email-jaz@semihalf.com> Message-ID: <1469105055-25181-8-git-send-email-jaz@semihalf.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Commit 1140011ee9d9 ("mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes") has extended the Device Tree binding used to describe PXAv3 SDHCI controllers in order to be able to use the SDR50 and DDR50 modes. This commit updates the Device Tree description of the Armada 39x SDHCI controller in other to take advantage of this functionality. Signed-off-by: Grzegorz Jaszczyk --- arch/arm/boot/dts/armada-39x.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index dc6efd3..cb66f20 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -380,7 +380,10 @@ sdhci at d8000 { compatible = "marvell,armada-380-sdhci"; - reg = <0xd8000 0x1000>, <0xdc000 0x100>; + reg-names = "sdhci", "mbus", "conf-sdio3"; + reg = <0xd8000 0x1000>, + <0xdc000 0x100>, + <0x18454 0x4>; interrupts = ; clocks = <&gateclk 17>; mrvl,clk-delay-cycles = <0x1F>; -- 1.8.3.1