From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37644) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bQI8o-00014S-Fk for qemu-devel@nongnu.org; Thu, 21 Jul 2016 13:52:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bQI8n-00029D-F2 for qemu-devel@nongnu.org; Thu, 21 Jul 2016 13:52:10 -0400 Received: from mx1.redhat.com ([209.132.183.28]:42399) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bQI8n-000296-9R for qemu-devel@nongnu.org; Thu, 21 Jul 2016 13:52:09 -0400 Date: Thu, 21 Jul 2016 20:52:04 +0300 From: "Michael S. Tsirkin" Message-ID: <1469123413-20809-15-git-send-email-mst@redhat.com> References: <1469123413-20809-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1469123413-20809-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PULL v5 14/57] intel_iommu: allow queued invalidation for IR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Peter Xu , Paolo Bonzini , Richard Henderson , Eduardo Habkost From: Peter Xu Queued invalidation is required for IR. This patch add basic support for interrupt cache invalidate requests. Since we currently have no IR cache implemented yet, we can just skip all interrupt cache invalidation requests for now. Signed-off-by: Peter Xu Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/intel_iommu.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e5f514c..b648e69 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -286,6 +286,8 @@ typedef struct VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_TYPE 0xf #define VTD_INV_DESC_CC 0x1 /* Context-cache Invalidate Desc */ #define VTD_INV_DESC_IOTLB 0x2 +#define VTD_INV_DESC_IEC 0x4 /* Interrupt Entry Cache + Invalidate Descriptor */ #define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descriptor */ #define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descriptor */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3ee5782..26e322a 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1404,6 +1404,15 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; + case VTD_INV_DESC_IEC: + VTD_DPRINTF(INV, "Interrupt Entry Cache Invalidation " + "not implemented yet"); + /* + * Since currently we do not cache interrupt entries, we can + * just mark this descriptor as "good" and move on. + */ + break; + default: VTD_DPRINTF(GENERAL, "error: unkonw Invalidation Descriptor type " "hi 0x%"PRIx64 " lo 0x%"PRIx64 " type %"PRIu8, -- MST