From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754749AbcG0J01 (ORCPT ); Wed, 27 Jul 2016 05:26:27 -0400 Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:42187 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754062AbcG0J0T (ORCPT ); Wed, 27 Jul 2016 05:26:19 -0400 Message-ID: <1469611550.2470.22.camel@pengutronix.de> Subject: Re: [PATCH v2 2/3] drm/mediatek: enhance the HDMI driving current From: Philipp Zabel To: Bibby Hsieh Cc: David Airlie , Matthias Brugger , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Yingjoe Chen , Cawa Cheng , Daniel Kurtz , YT Shen , Thierry Reding , CK Hu , Mao Huang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sascha Hauer , Junzhi Zhao Date: Wed, 27 Jul 2016 11:25:50 +0200 In-Reply-To: <1469608292-6106-3-git-send-email-bibby.hsieh@mediatek.com> References: <1469608292-6106-1-git-send-email-bibby.hsieh@mediatek.com> <1469608292-6106-3-git-send-email-bibby.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:100:96de:80ff:fec2:9969 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Mittwoch, den 27.07.2016, 16:31 +0800 schrieb Bibby Hsieh: > From: Junzhi Zhao > > In order to improve 4K resolution performance, > we have to enhance the HDMI driving currend ^ Typo, s/currend/current/ Besides that, this patch looks good to me. regards Philipp > when clock rate is greater than 165MHz. > > Signed-off-by: Junzhi Zhao > Signed-off-by: Bibby Hsieh > --- > drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 42 +++++++++++++++++------- > 1 file changed, 30 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > index 8a24754..51cb9cf 100644 > --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > @@ -265,6 +265,9 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); > unsigned int pre_div; > unsigned int div; > + unsigned int pre_ibias; > + unsigned int hdmi_ibias; > + unsigned int imp_en; > > dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, > rate, parent_rate); > @@ -298,18 +301,31 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > (0x1 << PLL_BR_SHIFT), > RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | > RG_HDMITX_PLL_BR); > - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN); > + if (rate < 165000000) { > + mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, > + RG_HDMITX_PRD_IMP_EN); > + pre_ibias = 0x3; > + imp_en = 0x0; > + hdmi_ibias = hdmi_phy->ibias; > + } else { > + mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, > + RG_HDMITX_PRD_IMP_EN); > + pre_ibias = 0x6; > + imp_en = 0xf; > + hdmi_ibias = hdmi_phy->ibias_up; > + } > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, > - (0x3 << PRD_IBIAS_CLK_SHIFT) | > - (0x3 << PRD_IBIAS_D2_SHIFT) | > - (0x3 << PRD_IBIAS_D1_SHIFT) | > - (0x3 << PRD_IBIAS_D0_SHIFT), > + (pre_ibias << PRD_IBIAS_CLK_SHIFT) | > + (pre_ibias << PRD_IBIAS_D2_SHIFT) | > + (pre_ibias << PRD_IBIAS_D1_SHIFT) | > + (pre_ibias << PRD_IBIAS_D0_SHIFT), > RG_HDMITX_PRD_IBIAS_CLK | > RG_HDMITX_PRD_IBIAS_D2 | > RG_HDMITX_PRD_IBIAS_D1 | > RG_HDMITX_PRD_IBIAS_D0); > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, > - (0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN); > + (imp_en << DRV_IMP_EN_SHIFT), > + RG_HDMITX_DRV_IMP_EN); > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, > (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | > (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | > @@ -318,12 +334,14 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | > RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, > - (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) | > - (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) | > - (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) | > - (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT), > - RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 | > - RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0); > + (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) | > + (hdmi_ibias << DRV_IBIAS_D2_SHIFT) | > + (hdmi_ibias << DRV_IBIAS_D1_SHIFT) | > + (hdmi_ibias << DRV_IBIAS_D0_SHIFT), > + RG_HDMITX_DRV_IBIAS_CLK | > + RG_HDMITX_DRV_IBIAS_D2 | > + RG_HDMITX_DRV_IBIAS_D1 | > + RG_HDMITX_DRV_IBIAS_D0); > return 0; > } > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philipp Zabel Subject: Re: [PATCH v2 2/3] drm/mediatek: enhance the HDMI driving current Date: Wed, 27 Jul 2016 11:25:50 +0200 Message-ID: <1469611550.2470.22.camel@pengutronix.de> References: <1469608292-6106-1-git-send-email-bibby.hsieh@mediatek.com> <1469608292-6106-3-git-send-email-bibby.hsieh@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1469608292-6106-3-git-send-email-bibby.hsieh@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Bibby Hsieh Cc: Junzhi Zhao , linux-kernel@vger.kernel.org, Daniel Vetter , Cawa Cheng , dri-devel@lists.freedesktop.org, Mao Huang , linux-mediatek@lists.infradead.org, Sascha Hauer , Matthias Brugger , Yingjoe Chen , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org QW0gTWl0dHdvY2gsIGRlbiAyNy4wNy4yMDE2LCAxNjozMSArMDgwMCBzY2hyaWViIEJpYmJ5IEhz aWVoOgo+IEZyb206IEp1bnpoaSBaaGFvIDxqdW56aGkuemhhb0BtZWRpYXRlay5jb20+Cj4gCj4g SW4gb3JkZXIgdG8gaW1wcm92ZSA0SyByZXNvbHV0aW9uIHBlcmZvcm1hbmNlLAo+IHdlIGhhdmUg dG8gZW5oYW5jZSB0aGUgSERNSSBkcml2aW5nIGN1cnJlbmQKICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgIF4KVHlwbywgcy9jdXJyZW5kL2N1cnJlbnQvCgpCZXNpZGVz IHRoYXQsIHRoaXMgcGF0Y2ggbG9va3MgZ29vZCB0byBtZS4KCnJlZ2FyZHMKUGhpbGlwcAoKPiB3 aGVuIGNsb2NrIHJhdGUgaXMgZ3JlYXRlciB0aGFuIDE2NU1Iei4KPiAKPiBTaWduZWQtb2ZmLWJ5 OiBKdW56aGkgWmhhbyA8anVuemhpLnpoYW9AbWVkaWF0ZWsuY29tPgo+IFNpZ25lZC1vZmYtYnk6 IEJpYmJ5IEhzaWVoIDxiaWJieS5oc2llaEBtZWRpYXRlay5jb20+Cj4gLS0tCj4gIGRyaXZlcnMv Z3B1L2RybS9tZWRpYXRlay9tdGtfbXQ4MTczX2hkbWlfcGh5LmMgfCAgIDQyICsrKysrKysrKysr KysrKysrLS0tLS0tLQo+ICAxIGZpbGUgY2hhbmdlZCwgMzAgaW5zZXJ0aW9ucygrKSwgMTIgZGVs ZXRpb25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtf bXQ4MTczX2hkbWlfcGh5LmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX210ODE3M19o ZG1pX3BoeS5jCj4gaW5kZXggOGEyNDc1NC4uNTFjYjljZiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJz L2dwdS9kcm0vbWVkaWF0ZWsvbXRrX210ODE3M19oZG1pX3BoeS5jCj4gKysrIGIvZHJpdmVycy9n cHUvZHJtL21lZGlhdGVrL210a19tdDgxNzNfaGRtaV9waHkuYwo+IEBAIC0yNjUsNiArMjY1LDkg QEAgc3RhdGljIGludCBtdGtfaGRtaV9wbGxfc2V0X3JhdGUoc3RydWN0IGNsa19odyAqaHcsIHVu c2lnbmVkIGxvbmcgcmF0ZSwKPiAgCXN0cnVjdCBtdGtfaGRtaV9waHkgKmhkbWlfcGh5ID0gdG9f bXRrX2hkbWlfcGh5KGh3KTsKPiAgCXVuc2lnbmVkIGludCBwcmVfZGl2Owo+ICAJdW5zaWduZWQg aW50IGRpdjsKPiArCXVuc2lnbmVkIGludCBwcmVfaWJpYXM7Cj4gKwl1bnNpZ25lZCBpbnQgaGRt aV9pYmlhczsKPiArCXVuc2lnbmVkIGludCBpbXBfZW47Cj4gIAo+ICAJZGV2X2RiZyhoZG1pX3Bo eS0+ZGV2LCAiJXM6ICVsdSBIeiwgcGFyZW50OiAlbHUgSHpcbiIsIF9fZnVuY19fLAo+ICAJCXJh dGUsIHBhcmVudF9yYXRlKTsKPiBAQCAtMjk4LDE4ICszMDEsMzEgQEAgc3RhdGljIGludCBtdGtf aGRtaV9wbGxfc2V0X3JhdGUoc3RydWN0IGNsa19odyAqaHcsIHVuc2lnbmVkIGxvbmcgcmF0ZSwK PiAgCQkJICAoMHgxIDw8IFBMTF9CUl9TSElGVCksCj4gIAkJCSAgUkdfSERNSVRYX1BMTF9CUCB8 IFJHX0hETUlUWF9QTExfQkMgfAo+ICAJCQkgIFJHX0hETUlUWF9QTExfQlIpOwo+IC0JbXRrX2hk bWlfcGh5X2NsZWFyX2JpdHMoaGRtaV9waHksIEhETUlfQ09OMywgUkdfSERNSVRYX1BSRF9JTVBf RU4pOwo+ICsJaWYgKHJhdGUgPCAxNjUwMDAwMDApIHsKPiArCQltdGtfaGRtaV9waHlfY2xlYXJf Yml0cyhoZG1pX3BoeSwgSERNSV9DT04zLAo+ICsJCQkJCVJHX0hETUlUWF9QUkRfSU1QX0VOKTsK PiArCQlwcmVfaWJpYXMgPSAweDM7Cj4gKwkJaW1wX2VuID0gMHgwOwo+ICsJCWhkbWlfaWJpYXMg PSBoZG1pX3BoeS0+aWJpYXM7Cj4gKwl9IGVsc2Ugewo+ICsJCW10a19oZG1pX3BoeV9zZXRfYml0 cyhoZG1pX3BoeSwgSERNSV9DT04zLAo+ICsJCQkJICAgICAgUkdfSERNSVRYX1BSRF9JTVBfRU4p Owo+ICsJCXByZV9pYmlhcyA9IDB4NjsKPiArCQlpbXBfZW4gPSAweGY7Cj4gKwkJaGRtaV9pYmlh cyA9IGhkbWlfcGh5LT5pYmlhc191cDsKPiArCX0KPiAgCW10a19oZG1pX3BoeV9tYXNrKGhkbWlf cGh5LCBIRE1JX0NPTjQsCj4gLQkJCSAgKDB4MyA8PCBQUkRfSUJJQVNfQ0xLX1NISUZUKSB8Cj4g LQkJCSAgKDB4MyA8PCBQUkRfSUJJQVNfRDJfU0hJRlQpIHwKPiAtCQkJICAoMHgzIDw8IFBSRF9J QklBU19EMV9TSElGVCkgfAo+IC0JCQkgICgweDMgPDwgUFJEX0lCSUFTX0QwX1NISUZUKSwKPiAr CQkJICAocHJlX2liaWFzIDw8IFBSRF9JQklBU19DTEtfU0hJRlQpIHwKPiArCQkJICAocHJlX2li aWFzIDw8IFBSRF9JQklBU19EMl9TSElGVCkgfAo+ICsJCQkgIChwcmVfaWJpYXMgPDwgUFJEX0lC SUFTX0QxX1NISUZUKSB8Cj4gKwkJCSAgKHByZV9pYmlhcyA8PCBQUkRfSUJJQVNfRDBfU0hJRlQp LAo+ICAJCQkgIFJHX0hETUlUWF9QUkRfSUJJQVNfQ0xLIHwKPiAgCQkJICBSR19IRE1JVFhfUFJE X0lCSUFTX0QyIHwKPiAgCQkJICBSR19IRE1JVFhfUFJEX0lCSUFTX0QxIHwKPiAgCQkJICBSR19I RE1JVFhfUFJEX0lCSUFTX0QwKTsKPiAgCW10a19oZG1pX3BoeV9tYXNrKGhkbWlfcGh5LCBIRE1J X0NPTjMsCj4gLQkJCSAgKDB4MCA8PCBEUlZfSU1QX0VOX1NISUZUKSwgUkdfSERNSVRYX0RSVl9J TVBfRU4pOwo+ICsJCQkgIChpbXBfZW4gPDwgRFJWX0lNUF9FTl9TSElGVCksCj4gKwkJCSAgUkdf SERNSVRYX0RSVl9JTVBfRU4pOwo+ICAJbXRrX2hkbWlfcGh5X21hc2soaGRtaV9waHksIEhETUlf Q09ONiwKPiAgCQkJICAoaGRtaV9waHktPmRydl9pbXBfY2xrIDw8IERSVl9JTVBfQ0xLX1NISUZU KSB8Cj4gIAkJCSAgKGhkbWlfcGh5LT5kcnZfaW1wX2QyIDw8IERSVl9JTVBfRDJfU0hJRlQpIHwK PiBAQCAtMzE4LDEyICszMzQsMTQgQEAgc3RhdGljIGludCBtdGtfaGRtaV9wbGxfc2V0X3JhdGUo c3RydWN0IGNsa19odyAqaHcsIHVuc2lnbmVkIGxvbmcgcmF0ZSwKPiAgCQkJICBSR19IRE1JVFhf RFJWX0lNUF9DTEsgfCBSR19IRE1JVFhfRFJWX0lNUF9EMiB8Cj4gIAkJCSAgUkdfSERNSVRYX0RS Vl9JTVBfRDEgfCBSR19IRE1JVFhfRFJWX0lNUF9EMCk7Cj4gIAltdGtfaGRtaV9waHlfbWFzayho ZG1pX3BoeSwgSERNSV9DT041LAo+IC0JCQkgIChoZG1pX3BoeS0+aWJpYXMgPDwgRFJWX0lCSUFT X0NMS19TSElGVCkgfAo+IC0JCQkgIChoZG1pX3BoeS0+aWJpYXMgPDwgRFJWX0lCSUFTX0QyX1NI SUZUKSB8Cj4gLQkJCSAgKGhkbWlfcGh5LT5pYmlhcyA8PCBEUlZfSUJJQVNfRDFfU0hJRlQpIHwK PiAtCQkJICAoaGRtaV9waHktPmliaWFzIDw8IERSVl9JQklBU19EMF9TSElGVCksCj4gLQkJCSAg UkdfSERNSVRYX0RSVl9JQklBU19DTEsgfCBSR19IRE1JVFhfRFJWX0lCSUFTX0QyIHwKPiAtCQkJ ICBSR19IRE1JVFhfRFJWX0lCSUFTX0QxIHwgUkdfSERNSVRYX0RSVl9JQklBU19EMCk7Cj4gKwkJ CSAgKGhkbWlfaWJpYXMgPDwgRFJWX0lCSUFTX0NMS19TSElGVCkgfAo+ICsJCQkgIChoZG1pX2li aWFzIDw8IERSVl9JQklBU19EMl9TSElGVCkgfAo+ICsJCQkgIChoZG1pX2liaWFzIDw8IERSVl9J QklBU19EMV9TSElGVCkgfAo+ICsJCQkgIChoZG1pX2liaWFzIDw8IERSVl9JQklBU19EMF9TSElG VCksCj4gKwkJCSAgUkdfSERNSVRYX0RSVl9JQklBU19DTEsgfAo+ICsJCQkgIFJHX0hETUlUWF9E UlZfSUJJQVNfRDIgfAo+ICsJCQkgIFJHX0hETUlUWF9EUlZfSUJJQVNfRDEgfAo+ICsJCQkgIFJH X0hETUlUWF9EUlZfSUJJQVNfRDApOwo+ICAJcmV0dXJuIDA7Cj4gIH0KPiAgCgoKX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcg bGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRl c2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: p.zabel@pengutronix.de (Philipp Zabel) Date: Wed, 27 Jul 2016 11:25:50 +0200 Subject: [PATCH v2 2/3] drm/mediatek: enhance the HDMI driving current In-Reply-To: <1469608292-6106-3-git-send-email-bibby.hsieh@mediatek.com> References: <1469608292-6106-1-git-send-email-bibby.hsieh@mediatek.com> <1469608292-6106-3-git-send-email-bibby.hsieh@mediatek.com> Message-ID: <1469611550.2470.22.camel@pengutronix.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Am Mittwoch, den 27.07.2016, 16:31 +0800 schrieb Bibby Hsieh: > From: Junzhi Zhao > > In order to improve 4K resolution performance, > we have to enhance the HDMI driving currend ^ Typo, s/currend/current/ Besides that, this patch looks good to me. regards Philipp > when clock rate is greater than 165MHz. > > Signed-off-by: Junzhi Zhao > Signed-off-by: Bibby Hsieh > --- > drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 42 +++++++++++++++++------- > 1 file changed, 30 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > index 8a24754..51cb9cf 100644 > --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > @@ -265,6 +265,9 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); > unsigned int pre_div; > unsigned int div; > + unsigned int pre_ibias; > + unsigned int hdmi_ibias; > + unsigned int imp_en; > > dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, > rate, parent_rate); > @@ -298,18 +301,31 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > (0x1 << PLL_BR_SHIFT), > RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | > RG_HDMITX_PLL_BR); > - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN); > + if (rate < 165000000) { > + mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, > + RG_HDMITX_PRD_IMP_EN); > + pre_ibias = 0x3; > + imp_en = 0x0; > + hdmi_ibias = hdmi_phy->ibias; > + } else { > + mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, > + RG_HDMITX_PRD_IMP_EN); > + pre_ibias = 0x6; > + imp_en = 0xf; > + hdmi_ibias = hdmi_phy->ibias_up; > + } > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, > - (0x3 << PRD_IBIAS_CLK_SHIFT) | > - (0x3 << PRD_IBIAS_D2_SHIFT) | > - (0x3 << PRD_IBIAS_D1_SHIFT) | > - (0x3 << PRD_IBIAS_D0_SHIFT), > + (pre_ibias << PRD_IBIAS_CLK_SHIFT) | > + (pre_ibias << PRD_IBIAS_D2_SHIFT) | > + (pre_ibias << PRD_IBIAS_D1_SHIFT) | > + (pre_ibias << PRD_IBIAS_D0_SHIFT), > RG_HDMITX_PRD_IBIAS_CLK | > RG_HDMITX_PRD_IBIAS_D2 | > RG_HDMITX_PRD_IBIAS_D1 | > RG_HDMITX_PRD_IBIAS_D0); > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, > - (0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN); > + (imp_en << DRV_IMP_EN_SHIFT), > + RG_HDMITX_DRV_IMP_EN); > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, > (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | > (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | > @@ -318,12 +334,14 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | > RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, > - (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) | > - (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) | > - (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) | > - (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT), > - RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 | > - RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0); > + (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) | > + (hdmi_ibias << DRV_IBIAS_D2_SHIFT) | > + (hdmi_ibias << DRV_IBIAS_D1_SHIFT) | > + (hdmi_ibias << DRV_IBIAS_D0_SHIFT), > + RG_HDMITX_DRV_IBIAS_CLK | > + RG_HDMITX_DRV_IBIAS_D2 | > + RG_HDMITX_DRV_IBIAS_D1 | > + RG_HDMITX_DRV_IBIAS_D0); > return 0; > } >