From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759464AbcG1Df3 (ORCPT ); Wed, 27 Jul 2016 23:35:29 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:9018 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1758866AbcG1DfZ (ORCPT ); Wed, 27 Jul 2016 23:35:25 -0400 Message-ID: <1469676916.29230.4.camel@mtksdaap41> Subject: Re: [PATCH v2 2/3] drm/mediatek: enhance the HDMI driving current From: Bibby Hsieh To: Philipp Zabel CC: David Airlie , Matthias Brugger , Daniel Vetter , , , Yingjoe Chen , Cawa Cheng , Daniel Kurtz , YT Shen , Thierry Reding , CK Hu , Mao Huang , , , "Sascha Hauer" , Junzhi Zhao Date: Thu, 28 Jul 2016 11:35:16 +0800 In-Reply-To: <1469611550.2470.22.camel@pengutronix.de> References: <1469608292-6106-1-git-send-email-bibby.hsieh@mediatek.com> <1469608292-6106-3-git-send-email-bibby.hsieh@mediatek.com> <1469611550.2470.22.camel@pengutronix.de> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Philipp, Thanks for your review. On Wed, 2016-07-27 at 11:25 +0200, Philipp Zabel wrote: > Am Mittwoch, den 27.07.2016, 16:31 +0800 schrieb Bibby Hsieh: > > From: Junzhi Zhao > > > > In order to improve 4K resolution performance, > > we have to enhance the HDMI driving currend > ^ > Typo, s/currend/current/ > > Besides that, this patch looks good to me. > Ok, I will fix that, thanks. > regards > Philipp > > > when clock rate is greater than 165MHz. > > > > Signed-off-by: Junzhi Zhao > > Signed-off-by: Bibby Hsieh > > --- > > drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 42 +++++++++++++++++------- > > 1 file changed, 30 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > > index 8a24754..51cb9cf 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > > +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > > @@ -265,6 +265,9 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > > struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); > > unsigned int pre_div; > > unsigned int div; > > + unsigned int pre_ibias; > > + unsigned int hdmi_ibias; > > + unsigned int imp_en; > > > > dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, > > rate, parent_rate); > > @@ -298,18 +301,31 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > > (0x1 << PLL_BR_SHIFT), > > RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | > > RG_HDMITX_PLL_BR); > > - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN); > > + if (rate < 165000000) { > > + mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, > > + RG_HDMITX_PRD_IMP_EN); > > + pre_ibias = 0x3; > > + imp_en = 0x0; > > + hdmi_ibias = hdmi_phy->ibias; > > + } else { > > + mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, > > + RG_HDMITX_PRD_IMP_EN); > > + pre_ibias = 0x6; > > + imp_en = 0xf; > > + hdmi_ibias = hdmi_phy->ibias_up; > > + } > > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, > > - (0x3 << PRD_IBIAS_CLK_SHIFT) | > > - (0x3 << PRD_IBIAS_D2_SHIFT) | > > - (0x3 << PRD_IBIAS_D1_SHIFT) | > > - (0x3 << PRD_IBIAS_D0_SHIFT), > > + (pre_ibias << PRD_IBIAS_CLK_SHIFT) | > > + (pre_ibias << PRD_IBIAS_D2_SHIFT) | > > + (pre_ibias << PRD_IBIAS_D1_SHIFT) | > > + (pre_ibias << PRD_IBIAS_D0_SHIFT), > > RG_HDMITX_PRD_IBIAS_CLK | > > RG_HDMITX_PRD_IBIAS_D2 | > > RG_HDMITX_PRD_IBIAS_D1 | > > RG_HDMITX_PRD_IBIAS_D0); > > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, > > - (0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN); > > + (imp_en << DRV_IMP_EN_SHIFT), > > + RG_HDMITX_DRV_IMP_EN); > > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, > > (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | > > (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | > > @@ -318,12 +334,14 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > > RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | > > RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); > > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, > > - (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) | > > - (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) | > > - (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) | > > - (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT), > > - RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 | > > - RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0); > > + (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) | > > + (hdmi_ibias << DRV_IBIAS_D2_SHIFT) | > > + (hdmi_ibias << DRV_IBIAS_D1_SHIFT) | > > + (hdmi_ibias << DRV_IBIAS_D0_SHIFT), > > + RG_HDMITX_DRV_IBIAS_CLK | > > + RG_HDMITX_DRV_IBIAS_D2 | > > + RG_HDMITX_DRV_IBIAS_D1 | > > + RG_HDMITX_DRV_IBIAS_D0); > > return 0; > > } > > > > -- Bibby From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bibby Hsieh Subject: Re: [PATCH v2 2/3] drm/mediatek: enhance the HDMI driving current Date: Thu, 28 Jul 2016 11:35:16 +0800 Message-ID: <1469676916.29230.4.camel@mtksdaap41> References: <1469608292-6106-1-git-send-email-bibby.hsieh@mediatek.com> <1469608292-6106-3-git-send-email-bibby.hsieh@mediatek.com> <1469611550.2470.22.camel@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1469611550.2470.22.camel@pengutronix.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Philipp Zabel Cc: Junzhi Zhao , linux-kernel@vger.kernel.org, Daniel Vetter , Cawa Cheng , dri-devel@lists.freedesktop.org, Mao Huang , linux-mediatek@lists.infradead.org, Sascha Hauer , Matthias Brugger , Yingjoe Chen , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org SGksIFBoaWxpcHAsCgpUaGFua3MgZm9yIHlvdXIgcmV2aWV3LgoKT24gV2VkLCAyMDE2LTA3LTI3 IGF0IDExOjI1ICswMjAwLCBQaGlsaXBwIFphYmVsIHdyb3RlOgo+IEFtIE1pdHR3b2NoLCBkZW4g MjcuMDcuMjAxNiwgMTY6MzEgKzA4MDAgc2NocmllYiBCaWJieSBIc2llaDoKPiA+IEZyb206IEp1 bnpoaSBaaGFvIDxqdW56aGkuemhhb0BtZWRpYXRlay5jb20+Cj4gPiAKPiA+IEluIG9yZGVyIHRv IGltcHJvdmUgNEsgcmVzb2x1dGlvbiBwZXJmb3JtYW5jZSwKPiA+IHdlIGhhdmUgdG8gZW5oYW5j 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X19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVs QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWls bWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: bibby.hsieh@mediatek.com (Bibby Hsieh) Date: Thu, 28 Jul 2016 11:35:16 +0800 Subject: [PATCH v2 2/3] drm/mediatek: enhance the HDMI driving current In-Reply-To: <1469611550.2470.22.camel@pengutronix.de> References: <1469608292-6106-1-git-send-email-bibby.hsieh@mediatek.com> <1469608292-6106-3-git-send-email-bibby.hsieh@mediatek.com> <1469611550.2470.22.camel@pengutronix.de> Message-ID: <1469676916.29230.4.camel@mtksdaap41> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, Philipp, Thanks for your review. On Wed, 2016-07-27 at 11:25 +0200, Philipp Zabel wrote: > Am Mittwoch, den 27.07.2016, 16:31 +0800 schrieb Bibby Hsieh: > > From: Junzhi Zhao > > > > In order to improve 4K resolution performance, > > we have to enhance the HDMI driving currend > ^ > Typo, s/currend/current/ > > Besides that, this patch looks good to me. > Ok, I will fix that, thanks. > regards > Philipp > > > when clock rate is greater than 165MHz. > > > > Signed-off-by: Junzhi Zhao > > Signed-off-by: Bibby Hsieh > > --- > > drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 42 +++++++++++++++++------- > > 1 file changed, 30 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > > index 8a24754..51cb9cf 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > > +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > > @@ -265,6 +265,9 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > > struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); > > unsigned int pre_div; > > unsigned int div; > > + unsigned int pre_ibias; > > + unsigned int hdmi_ibias; > > + unsigned int imp_en; > > > > dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, > > rate, parent_rate); > > @@ -298,18 +301,31 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > > (0x1 << PLL_BR_SHIFT), > > RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | > > RG_HDMITX_PLL_BR); > > - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN); > > + if (rate < 165000000) { > > + mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, > > + RG_HDMITX_PRD_IMP_EN); > > + pre_ibias = 0x3; > > + imp_en = 0x0; > > + hdmi_ibias = hdmi_phy->ibias; > > + } else { > > + mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, > > + RG_HDMITX_PRD_IMP_EN); > > + pre_ibias = 0x6; > > + imp_en = 0xf; > > + hdmi_ibias = hdmi_phy->ibias_up; > > + } > > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, > > - (0x3 << PRD_IBIAS_CLK_SHIFT) | > > - (0x3 << PRD_IBIAS_D2_SHIFT) | > > - (0x3 << PRD_IBIAS_D1_SHIFT) | > > - (0x3 << PRD_IBIAS_D0_SHIFT), > > + (pre_ibias << PRD_IBIAS_CLK_SHIFT) | > > + (pre_ibias << PRD_IBIAS_D2_SHIFT) | > > + (pre_ibias << PRD_IBIAS_D1_SHIFT) | > > + (pre_ibias << PRD_IBIAS_D0_SHIFT), > > RG_HDMITX_PRD_IBIAS_CLK | > > RG_HDMITX_PRD_IBIAS_D2 | > > RG_HDMITX_PRD_IBIAS_D1 | > > RG_HDMITX_PRD_IBIAS_D0); > > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, > > - (0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN); > > + (imp_en << DRV_IMP_EN_SHIFT), > > + RG_HDMITX_DRV_IMP_EN); > > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, > > (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | > > (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | > > @@ -318,12 +334,14 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > > RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | > > RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); > > mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, > > - (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) | > > - (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) | > > - (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) | > > - (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT), > > - RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 | > > - RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0); > > + (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) | > > + (hdmi_ibias << DRV_IBIAS_D2_SHIFT) | > > + (hdmi_ibias << DRV_IBIAS_D1_SHIFT) | > > + (hdmi_ibias << DRV_IBIAS_D0_SHIFT), > > + RG_HDMITX_DRV_IBIAS_CLK | > > + RG_HDMITX_DRV_IBIAS_D2 | > > + RG_HDMITX_DRV_IBIAS_D1 | > > + RG_HDMITX_DRV_IBIAS_D0); > > return 0; > > } > > > > -- Bibby