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Subject: Re: [PATCH v5 07/10] drm/mediatek: add dsi transfer function
From: YT Shen <yt.shen@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>
CC: <dri-devel@lists.freedesktop.org>, Philipp Zabel <p.zabel@pengutronix.de>,
        Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
        "Mark Rutland" <mark.rutland@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        Kumar Gala <galak@codeaurora.org>,
        "Russell King" <linux@arm.linux.org.uk>,
        David Airlie <airlied@linux.ie>,
        "Matthias Brugger" <matthias.bgg@gmail.com>,
        Mao Huang <littlecvr@chromium.org>,
        "Bibby Hsieh" <bibby.hsieh@mediatek.com>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,
        <linux-mediatek@lists.infradead.org>, <srv_heupstream@mediatek.com>,
        "Sascha Hauer" <kernel@pengutronix.de>, <yingjoe.chen@mediatek.com>,
        <emil.l.velikov@gmail.com>, <thierry.reding@gmail.com>,
        shaoming chen <shaoming.chen@mediatek.com>
Date: Tue, 2 Aug 2016 17:14:48 +0800
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References: <1469698084-20185-1-git-send-email-yt.shen@mediatek.com>
	 <1469698084-20185-8-git-send-email-yt.shen@mediatek.com>
	 <1470120958.16554.16.camel@mtksdaap41>
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Hi CK,

On Tue, 2016-08-02 at 14:55 +0800, CK Hu wrote:
> Hi, YT:
> 
> On Thu, 2016-07-28 at 17:28 +0800, YT Shen wrote:
> > From: shaoming chen <shaoming.chen@mediatek.com>
> > 
> > add dsi read/write commands for transfer function
> > 
> > Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_dsi.c |  286 ++++++++++++++++++++++++++++++++++++
> >  1 file changed, 286 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 553443a..1d36524 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -24,6 +24,7 @@
> >  #include <linux/of_graph.h>
> >  #include <linux/phy/phy.h>
> >  #include <linux/platform_device.h>
> > +#include <video/mipi_display.h>
> >  #include <video/videomode.h>
> >  
> >  #include "mtk_drm_ddp_comp.h"
> > @@ -81,8 +82,16 @@
> >  #define DSI_HBP_WC		0x54
> >  #define DSI_HFP_WC		0x58
> >  
> > +#define DSI_CMDQ_SIZE		0x60
> > +#define CMDQ_SIZE		0x3f
> > +
> >  #define DSI_HSTX_CKL_WC		0x64
> >  
> > +#define DSI_RX_DATA0		0x74
> > +#define DSI_RX_DATA1		0x78
> > +#define DSI_RX_DATA2		0x7c
> > +#define DSI_RX_DATA3		0x80
> > +
> >  #define DSI_RACK		0x84
> >  #define RACK				BIT(0)
> >  
> > @@ -118,8 +127,25 @@
> >  #define CLK_HS_POST			(0xff << 8)
> >  #define CLK_HS_EXIT			(0xff << 16)
> >  
> > +#define DSI_CMDQ0		0x180
> > +
> >  #define NS_TO_CYCLE(n, c)    ((n) / (c) + (((n) % (c)) ? 1 : 0))
> >  
> > +#define MTK_DSI_HOST_IS_READ(type) \
> > +	((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
> > +	(type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
> > +	(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
> > +	(type == MIPI_DSI_DCS_READ))
> > +
> > +#define MTK_DSI_HOST_IS_WRITE(type) \
> > +	((type == MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM) || \
> > +	(type == MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM) || \
> > +	(type == MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM) || \
> > +	(type == MIPI_DSI_DCS_SHORT_WRITE) || \
> > +	(type == MIPI_DSI_DCS_SHORT_WRITE_PARAM) || \
> > +	(type == MIPI_DSI_GENERIC_LONG_WRITE) || \
> > +	(type == MIPI_DSI_DCS_LONG_WRITE))
> > +
> >  struct phy;
> >  
> >  struct mtk_dsi {
> > @@ -149,6 +175,17 @@ struct mtk_dsi {
> >  	int irq_data;
> >  };
> >  
> > +struct dsi_rxtx_data {
> > +	u8 byte0;
> > +	u8 byte1;
> > +	u8 byte2;
> > +	u8 byte3;
> > +};
> > +
> > +struct dsi_tx_cmdq_regs {
> > +	struct dsi_rxtx_data data[128];
> > +};
> > +
> >  static wait_queue_head_t _dsi_cmd_done_wait_queue;
> >  static wait_queue_head_t _dsi_dcs_read_wait_queue;
> >  static wait_queue_head_t _dsi_wait_vm_done_queue;
> > @@ -813,9 +850,258 @@ static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
> >  	return 0;
> >  }
> >  
> > +static void mtk_dsi_set_cmdq(void __iomem *reg, u32 mask, u32 data)
> > +{
> > +	u32 temp = readl(reg);
> > +
> > +	writel((temp & ~mask) | (data & mask), reg);
> > +}
> > +
> > +static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
> > +{
> > +	u32 timeout_ms = 500000; /* total 1s ~ 2s timeout */
> > +
> > +	while (timeout_ms--) {
> > +		if (!(readl(dsi->regs + DSI_INTSTA) & DSI_BUSY))
> > +			break;
> > +
> > +		usleep_range(2, 4);
> > +	}
> > +
> > +	if (timeout_ms == 0) {
> > +		dev_info(dsi->dev, "polling dsi wait not busy timeout!\n");
> > +
> > +		mtk_dsi_enable(dsi);
> > +		mtk_dsi_reset_engine(dsi);
> > +	}
> > +}
> > +
> > +static void mtk_dsi_wait_for_cmd_done(struct mtk_dsi *dsi)
> > +{
> > +	s32 ret = 0;
> > +	unsigned long timeout = msecs_to_jiffies(500);
> > +
> > +	ret = wait_event_interruptible_timeout(_dsi_cmd_done_wait_queue,
> > +			dsi->irq_data & CMD_DONE_INT_FLAG, timeout);
> > +	if (ret == 0) {
> > +		dev_info(dsi->dev, "dsi wait engine cmd done fail\n");
> > +		mtk_dsi_enable(dsi);
> > +		mtk_dsi_reset_engine(dsi);
> > +		return;
> > +	}
> > +
> > +	dsi->irq_data &= ~CMD_DONE_INT_FLAG;
> 
> I think you should move this before trigger HW. Sometimes this interrupt
> is coming and this flag is set but you do not wait this event and do not
> clear it. Then when you want to wait, the flag is already set by long
> time ago interrupt.
OK, we will fix it.

> 
> > +}
> > +
> > +static ssize_t mtk_dsi_host_read_cmd(struct mtk_dsi *dsi,
> > +				     const struct mipi_dsi_msg *msg)
> > +{
> > +	u8 max_try_count = 5;
> > +	u32 recv_cnt, tmp_val;
> > +	struct dsi_rxtx_data read_data0, read_data1, read_data2, read_data3;
> > +	u8 config, type, data0, data1;
> > +	s32 ret;
> > +
> > +	u8 *buffer = msg->rx_buf;
> > +	u8 buffer_size = msg->rx_len;
> > +
> > +	if (readl(dsi->regs + DSI_MODE_CTRL) & 0x03) {
> > +		dev_info(dsi->dev, "dsi engine is not command mode\n");
> > +		return -1;
> > +	}
> > +
> > +	if (!buffer) {
> > +		dev_info(dsi->dev, "dsi receive buffer size may be NULL\n");
> > +		return -1;
> > +	}
> > +
> > +	do {
> > +		if (max_try_count == 0) {
> > +			dev_info(dsi->dev, "dsi engine read counter has been maxinum\n");
> > +			return -1;
> > +		}
> > +
> > +		max_try_count--;
> > +		recv_cnt = 0;
> > +
> > +		mtk_dsi_wait_for_idle(dsi);
> > +
> > +		config = 0x04;
> > +		data0 = *((u8 *)(msg->tx_buf));
> > +
> > +		if (buffer_size < 3)
> > +			type = MIPI_DSI_DCS_READ;
> > +		else
> > +			type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
> > +
> > +		data1 = 0;
> > +
> > +		tmp_val = (data1 << 24) | (data0 << 16) | (type << 8) | config;
> > +
> > +		writel(tmp_val, dsi->regs + DSI_CMDQ0);
> > +		mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, 1);
> > +
> > +		mtk_dsi_start(dsi);
> 
> This part looks like the same as mtk_dsi_host_write_cmd() with
> msg->tx_len = 1. Maybe you can try to merge these two part.
Will do.

> 
> > +
> > +		/* 2s timeout*/
> > +		ret = wait_event_interruptible_timeout(_dsi_dcs_read_wait_queue,
> > +				dsi->irq_data & LPRX_RD_RDY_INT_FLAG, timeout);
> > +		if (ret == 0) {
> > +			dev_info(dsi->dev, "Wait DSI read ready timeout!!!\n");
> > +
> > +			mtk_dsi_enable(dsi);
> > +			mtk_dsi_reset_engine(dsi);
> > +
> > +			return ret;
> > +		}
> > +
> > +		dsi->irq_data &= ~LPRX_RD_RDY_INT_FLAG;
> 
> I think you should move this before trigger HW. Sometimes this interrupt
> is coming and this flag is set but you do not wait this event and do not
> clear it. Then when you want to wait, the flag is already set by long
> time ago interrupt.
Will do.

> 
> > +
> > +		*(u32 *)(&read_data0) = readl(dsi->regs + DSI_RX_DATA0);
> > +		*(u32 *)(&read_data1) = readl(dsi->regs + DSI_RX_DATA1);
> > +		*(u32 *)(&read_data2) = readl(dsi->regs + DSI_RX_DATA2);
> > +		*(u32 *)(&read_data3) = readl(dsi->regs + DSI_RX_DATA3);
> > +
> > +		type = read_data0.byte0;
> > +
> > +		if (type == MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE ||
> > +		    type == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
> > +
> > +			/*
> > +			 * Data ID(1 byte) + Word Count(2 bytes) + ECC(1 byte) +
> > +			 * data 0 + ...+ data WC-1 + CHECKSUM (2 bytes)
> 
> Is CHECKSUM useless? Why not check it?
We will check this.

> 
> > +			 */
> > +			recv_cnt = read_data0.byte1 + read_data0.byte2 * 16;
> > +			dev_info(dsi->dev, "long packet size: %d\n", recv_cnt);
> > +
> > +			/*
> > +			 * the buffer size is 16 bytes once, so the data payload
> > +			 * is, 16 - bytes(data ID + WC + ECC + CHECKSUM), if
> > +			 * over 10 bytes, it will be read again
> > +			 */
> > +			if (recv_cnt > 10)
> > +				recv_cnt = 10;
> > +
> > +			if (recv_cnt > buffer_size)
> > +				recv_cnt = buffer_size;
> > +
> > +			if (recv_cnt <= 4) {
> > +				memcpy(buffer, &read_data1, recv_cnt);
> > +			} else if (recv_cnt <= 8) {
> > +				memcpy(buffer, &read_data1, 4);
> > +				memcpy(buffer + 4, &read_data2, recv_cnt - 4);
> > +			} else {
> > +				memcpy(buffer, &read_data1, 4);
> > +				memcpy(buffer + 4, &read_data2, 4);
> > +				memcpy(buffer + 8, &read_data3, recv_cnt - 8);
> > +			}
> 
> I think you can ignore read_data1, read_data2, and read_data3. Using a
> 'for loop' and readb() here can directly read register data into buffer.
We will rewrite this part.

> 
> 
> > +		} else if (type == MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE ||
> > +			   type == MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE ||
> > +			   type == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE ||
> > +			   type == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
> > +
> > +			if (type == MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE ||
> > +			    type == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)
> > +				recv_cnt = 1;
> > +			else
> > +				recv_cnt = 2;
> > +
> > +			if (recv_cnt > buffer_size)
> > +				recv_cnt = buffer_size;
> > +
> > +			memcpy(buffer, &read_data0.byte1, recv_cnt);
> > +		} else if (type == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
> > +			dev_info(dsi->dev, "packet type is 0x02, try again\n");
> > +		} else {
> > +			dev_info(dsi->dev, "packet type(0x%x) cannot be non-recognize\n",
> > +				 type);
> > +
> > +			return 0;
> > +		}
> > +	} while (type == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT);
> > +
> > +	dev_info(dsi->dev, "dsi get %d byte data from the panel address(0x%x)\n",
> > +		 recv_cnt, *((u8 *)(msg->tx_buf)));
> > +
> > +	return recv_cnt;
> > +}
> > +
> > +static ssize_t mtk_dsi_host_write_cmd(struct mtk_dsi *dsi,
> > +				      const struct mipi_dsi_msg *msg)
> > +{
> > +	u32 i;
> > +	u32 goto_addr, mask_para, set_para, reg_val;
> > +	void __iomem *cmdq_reg;
> > +	u8 config, type, data0, data1;
> > +	u16 wc16;
> > +	const char *tx_buf = msg->tx_buf;
> > +	struct dsi_tx_cmdq_regs *dsi_cmd_reg;
> > +
> > +	dsi_cmd_reg = (struct dsi_tx_cmdq_regs *)(dsi->regs + DSI_CMDQ0);
> > +
> > +	mtk_dsi_wait_for_idle(dsi);
> > +
> > +	if (msg->tx_len > 2) {
> > +		config = 2;
> > +		type = msg->type;
> > +		wc16 = msg->tx_len;
> > +
> > +		reg_val = (wc16 << 16) | (type << 8) | config;
> > +
> > +		writel(reg_val, &dsi_cmd_reg->data[0]);
> > +
> > +		for (i = 0; i < msg->tx_len; i++) {
> > +			goto_addr = (u32)(&dsi_cmd_reg->data[1].byte0) + i;
> > +			mask_para = (0xff << ((goto_addr & 0x3) * 8));
> > +			set_para = (tx_buf[i] << ((goto_addr & 0x3) * 8));
> > +			cmdq_reg = (void __iomem *)(goto_addr & (~0x3));
> > +			mtk_dsi_set_cmdq(cmdq_reg, mask_para, set_para);
> > +		}
> 
> Because you use writel(), so this part look so complicated. If you use
> writeb(), this would be much simpler.
OK, we will use writeb() in the next version.

Regards,
yt.shen

> 
> > +
> > +		mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE,
> > +			     1 + (msg->tx_len + 3) / 4);
> > +	} else {
> > +		config = 0;
> > +		data0 = tx_buf[0];
> > +		if (msg->tx_len == 2) {
> > +			type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
> > +			data1 = tx_buf[1];
> > +		} else {
> > +			type = MIPI_DSI_DCS_SHORT_WRITE;
> > +			data1 = 0;
> > +		}
> > +
> > +		reg_val = (data1 << 24) | (data0 << 16) | (type << 8) | config;
> > +
> > +		writel(reg_val, &dsi_cmd_reg->data[0]);
> > +		mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, 1);
> > +	}
> > +
> > +	mtk_dsi_start(dsi);
> > +	mtk_dsi_wait_for_cmd_done(dsi);
> > +
> > +	return 0;
> > +}
> > +
> > +static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
> > +				     const struct mipi_dsi_msg *msg)
> > +{
> > +	struct mtk_dsi *dsi = host_to_dsi(host);
> > +	u8 type = msg->type;
> > +	ssize_t ret = 0;
> > +
> > +	if (MTK_DSI_HOST_IS_READ(type))
> > +		ret = mtk_dsi_host_read_cmd(dsi, msg);
> > +	else if (MTK_DSI_HOST_IS_WRITE(type))
> > +		ret = mtk_dsi_host_write_cmd(dsi, msg);
> > +
> > +	return ret;
> > +}
> > +
> >  static const struct mipi_dsi_host_ops mtk_dsi_ops = {
> >  	.attach = mtk_dsi_host_attach,
> >  	.detach = mtk_dsi_host_detach,
> > +	.transfer = mtk_dsi_host_transfer,
> >  };
> >  
> >  static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
> 
> Regards,
> CK
> 

From mboxrd@z Thu Jan  1 00:00:00 1970
From: YT Shen <yt.shen@mediatek.com>
Subject: Re: [PATCH v5 07/10] drm/mediatek: add dsi transfer function
Date: Tue, 2 Aug 2016 17:14:48 +0800
Message-ID: <1470129288.30671.13.camel@mtksdaap41>
References: <1469698084-20185-1-git-send-email-yt.shen@mediatek.com>
 <1469698084-20185-8-git-send-email-yt.shen@mediatek.com>
 <1470120958.16554.16.camel@mtksdaap41>
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To: CK Hu <ck.hu@mediatek.com>
Cc: Mark Rutland <mark.rutland@arm.com>, dri-devel@lists.freedesktop.org, Russell King <linux@arm.linux.org.uk>, Mao Huang <littlecvr@chromium.org>, yingjoe.chen@mediatek.com, devicetree@vger.kernel.org, Sascha Hauer <kernel@pengutronix.de>, Pawel Moll <pawel.moll@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Rob Herring <robh+dt@kernel.org>, linux-mediatek@lists.infradead.org, Matthias Brugger <matthias.bgg@gmail.com>, shaoming chen <shaoming.chen@mediatek.com>, linux-arm-kernel@lists.infradead.org, srv_heupstream@mediatek.com, emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Kumar Gala <galak@codeaurora.org>
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SGkgQ0ssCgpPbiBUdWUsIDIwMTYtMDgtMDIgYXQgMTQ6NTUgKzA4MDAsIENLIEh1IHdyb3RlOgo+
IEhpLCBZVDoKPiAKPiBPbiBUaHUsIDIwMTYtMDctMjggYXQgMTc6MjggKzA4MDAsIFlUIFNoZW4g
d3JvdGU6Cj4gPiBGcm9tOiBzaGFvbWluZyBjaGVuIDxzaGFvbWluZy5jaGVuQG1lZGlhdGVrLmNv
bT4KPiA+IAo+ID4gYWRkIGRzaSByZWFkL3dyaXRlIGNvbW1hbmRzIGZvciB0cmFuc2ZlciBmdW5j
dGlvbgo+ID4gCj4gPiBTaWduZWQtb2ZmLWJ5OiBzaGFvbWluZyBjaGVuIDxzaGFvbWluZy5jaGVu
QG1lZGlhdGVrLmNvbT4KPiA+IC0tLQo+ID4gIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtf
ZHNpLmMgfCAgMjg2ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKwo+ID4gIDEg
ZmlsZSBjaGFuZ2VkLCAyODYgaW5zZXJ0aW9ucygrKQo+ID4gCj4gPiBkaWZmIC0tZ2l0IGEvZHJp
dmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kc2kuYyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRl
ay9tdGtfZHNpLmMKPiA+IGluZGV4IDU1MzQ0M2EuLjFkMzY1MjQgMTAwNjQ0Cj4gPiAtLS0gYS9k
cml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RzaS5jCj4gPiArKysgYi9kcml2ZXJzL2dwdS9k
cm0vbWVkaWF0ZWsvbXRrX2RzaS5jCj4gPiBAQCAtMjQsNiArMjQsNyBAQAo+ID4gICNpbmNsdWRl
IDxsaW51eC9vZl9ncmFwaC5oPgo+ID4gICNpbmNsdWRlIDxsaW51eC9waHkvcGh5Lmg+Cj4gPiAg
I2luY2x1ZGUgPGxpbnV4L3BsYXRmb3JtX2RldmljZS5oPgo+ID4gKyNpbmNsdWRlIDx2aWRlby9t
aXBpX2Rpc3BsYXkuaD4KPiA+ICAjaW5jbHVkZSA8dmlkZW8vdmlkZW9tb2RlLmg+Cj4gPiAgCj4g
PiAgI2luY2x1ZGUgIm10a19kcm1fZGRwX2NvbXAuaCIKPiA+IEBAIC04MSw4ICs4MiwxNiBAQAo+
ID4gICNkZWZpbmUgRFNJX0hCUF9XQwkJMHg1NAo+ID4gICNkZWZpbmUgRFNJX0hGUF9XQwkJMHg1
OAo+ID4gIAo+ID4gKyNkZWZpbmUgRFNJX0NNRFFfU0laRQkJMHg2MAo+ID4gKyNkZWZpbmUgQ01E
UV9TSVpFCQkweDNmCj4gPiArCj4gPiAgI2RlZmluZSBEU0lfSFNUWF9DS0xfV0MJCTB4NjQKPiA+
ICAKPiA+ICsjZGVmaW5lIERTSV9SWF9EQVRBMAkJMHg3NAo+ID4gKyNkZWZpbmUgRFNJX1JYX0RB
VEExCQkweDc4Cj4gPiArI2RlZmluZSBEU0lfUlhfREFUQTIJCTB4N2MKPiA+ICsjZGVmaW5lIERT
SV9SWF9EQVRBMwkJMHg4MAo+ID4gKwo+ID4gICNkZWZpbmUgRFNJX1JBQ0sJCTB4ODQKPiA+ICAj
ZGVmaW5lIFJBQ0sJCQkJQklUKDApCj4gPiAgCj4gPiBAQCAtMTE4LDggKzEyNywyNSBAQAo+ID4g
ICNkZWZpbmUgQ0xLX0hTX1BPU1QJCQkoMHhmZiA8PCA4KQo+ID4gICNkZWZpbmUgQ0xLX0hTX0VY
SVQJCQkoMHhmZiA8PCAxNikKPiA+ICAKPiA+ICsjZGVmaW5lIERTSV9DTURRMAkJMHgxODAKPiA+
ICsKPiA+ICAjZGVmaW5lIE5TX1RPX0NZQ0xFKG4sIGMpICAgICgobikgLyAoYykgKyAoKChuKSAl
IChjKSkgPyAxIDogMCkpCj4gPiAgCj4gPiArI2RlZmluZSBNVEtfRFNJX0hPU1RfSVNfUkVBRCh0
eXBlKSBcCj4gPiArCSgodHlwZSA9PSBNSVBJX0RTSV9HRU5FUklDX1JFQURfUkVRVUVTVF8wX1BB
UkFNKSB8fCBcCj4gPiArCSh0eXBlID09IE1JUElfRFNJX0dFTkVSSUNfUkVBRF9SRVFVRVNUXzFf
UEFSQU0pIHx8IFwKPiA+ICsJKHR5cGUgPT0gTUlQSV9EU0lfR0VORVJJQ19SRUFEX1JFUVVFU1Rf
Ml9QQVJBTSkgfHwgXAo+ID4gKwkodHlwZSA9PSBNSVBJX0RTSV9EQ1NfUkVBRCkpCj4gPiArCj4g
PiArI2RlZmluZSBNVEtfRFNJX0hPU1RfSVNfV1JJVEUodHlwZSkgXAo+ID4gKwkoKHR5cGUgPT0g
TUlQSV9EU0lfR0VORVJJQ19TSE9SVF9XUklURV8wX1BBUkFNKSB8fCBcCj4gPiArCSh0eXBlID09
IE1JUElfRFNJX0dFTkVSSUNfU0hPUlRfV1JJVEVfMV9QQVJBTSkgfHwgXAo+ID4gKwkodHlwZSA9
PSBNSVBJX0RTSV9HRU5FUklDX1NIT1JUX1dSSVRFXzJfUEFSQU0pIHx8IFwKPiA+ICsJKHR5cGUg
PT0gTUlQSV9EU0lfRENTX1NIT1JUX1dSSVRFKSB8fCBcCj4gPiArCSh0eXBlID09IE1JUElfRFNJ
X0RDU19TSE9SVF9XUklURV9QQVJBTSkgfHwgXAo+ID4gKwkodHlwZSA9PSBNSVBJX0RTSV9HRU5F
UklDX0xPTkdfV1JJVEUpIHx8IFwKPiA+ICsJKHR5cGUgPT0gTUlQSV9EU0lfRENTX0xPTkdfV1JJ
VEUpKQo+ID4gKwo+ID4gIHN0cnVjdCBwaHk7Cj4gPiAgCj4gPiAgc3RydWN0IG10a19kc2kgewo+
ID4gQEAgLTE0OSw2ICsxNzUsMTcgQEAgc3RydWN0IG10a19kc2kgewo+ID4gIAlpbnQgaXJxX2Rh
dGE7Cj4gPiAgfTsKPiA+ICAKPiA+ICtzdHJ1Y3QgZHNpX3J4dHhfZGF0YSB7Cj4gPiArCXU4IGJ5
dGUwOwo+ID4gKwl1OCBieXRlMTsKPiA+ICsJdTggYnl0ZTI7Cj4gPiArCXU4IGJ5dGUzOwo+ID4g
K307Cj4gPiArCj4gPiArc3RydWN0IGRzaV90eF9jbWRxX3JlZ3Mgewo+ID4gKwlzdHJ1Y3QgZHNp
X3J4dHhfZGF0YSBkYXRhWzEyOF07Cj4gPiArfTsKPiA+ICsKPiA+ICBzdGF0aWMgd2FpdF9xdWV1
ZV9oZWFkX3QgX2RzaV9jbWRfZG9uZV93YWl0X3F1ZXVlOwo+ID4gIHN0YXRpYyB3YWl0X3F1ZXVl
X2hlYWRfdCBfZHNpX2Rjc19yZWFkX3dhaXRfcXVldWU7Cj4gPiAgc3RhdGljIHdhaXRfcXVldWVf
aGVhZF90IF9kc2lfd2FpdF92bV9kb25lX3F1ZXVlOwo+ID4gQEAgLTgxMyw5ICs4NTAsMjU4IEBA
IHN0YXRpYyBpbnQgbXRrX2RzaV9ob3N0X2RldGFjaChzdHJ1Y3QgbWlwaV9kc2lfaG9zdCAqaG9z
dCwKPiA+ICAJcmV0dXJuIDA7Cj4gPiAgfQo+ID4gIAo+ID4gK3N0YXRpYyB2b2lkIG10a19kc2lf
c2V0X2NtZHEodm9pZCBfX2lvbWVtICpyZWcsIHUzMiBtYXNrLCB1MzIgZGF0YSkKPiA+ICt7Cj4g
PiArCXUzMiB0ZW1wID0gcmVhZGwocmVnKTsKPiA+ICsKPiA+ICsJd3JpdGVsKCh0ZW1wICYgfm1h
c2spIHwgKGRhdGEgJiBtYXNrKSwgcmVnKTsKPiA+ICt9Cj4gPiArCj4gPiArc3RhdGljIHZvaWQg
bXRrX2RzaV93YWl0X2Zvcl9pZGxlKHN0cnVjdCBtdGtfZHNpICpkc2kpCj4gPiArewo+ID4gKwl1
MzIgdGltZW91dF9tcyA9IDUwMDAwMDsgLyogdG90YWwgMXMgfiAycyB0aW1lb3V0ICovCj4gPiAr
Cj4gPiArCXdoaWxlICh0aW1lb3V0X21zLS0pIHsKPiA+ICsJCWlmICghKHJlYWRsKGRzaS0+cmVn
cyArIERTSV9JTlRTVEEpICYgRFNJX0JVU1kpKQo+ID4gKwkJCWJyZWFrOwo+ID4gKwo+ID4gKwkJ
dXNsZWVwX3JhbmdlKDIsIDQpOwo+ID4gKwl9Cj4gPiArCj4gPiArCWlmICh0aW1lb3V0X21zID09
IDApIHsKPiA+ICsJCWRldl9pbmZvKGRzaS0+ZGV2LCAicG9sbGluZyBkc2kgd2FpdCBub3QgYnVz
eSB0aW1lb3V0IVxuIik7Cj4gPiArCj4gPiArCQltdGtfZHNpX2VuYWJsZShkc2kpOwo+ID4gKwkJ
bXRrX2RzaV9yZXNldF9lbmdpbmUoZHNpKTsKPiA+ICsJfQo+ID4gK30KPiA+ICsKPiA+ICtzdGF0
aWMgdm9pZCBtdGtfZHNpX3dhaXRfZm9yX2NtZF9kb25lKHN0cnVjdCBtdGtfZHNpICpkc2kpCj4g
PiArewo+ID4gKwlzMzIgcmV0ID0gMDsKPiA+ICsJdW5zaWduZWQgbG9uZyB0aW1lb3V0ID0gbXNl
Y3NfdG9famlmZmllcyg1MDApOwo+ID4gKwo+ID4gKwlyZXQgPSB3YWl0X2V2ZW50X2ludGVycnVw
dGlibGVfdGltZW91dChfZHNpX2NtZF9kb25lX3dhaXRfcXVldWUsCj4gPiArCQkJZHNpLT5pcnFf
ZGF0YSAmIENNRF9ET05FX0lOVF9GTEFHLCB0aW1lb3V0KTsKPiA+ICsJaWYgKHJldCA9PSAwKSB7
Cj4gPiArCQlkZXZfaW5mbyhkc2ktPmRldiwgImRzaSB3YWl0IGVuZ2luZSBjbWQgZG9uZSBmYWls
XG4iKTsKPiA+ICsJCW10a19kc2lfZW5hYmxlKGRzaSk7Cj4gPiArCQltdGtfZHNpX3Jlc2V0X2Vu
Z2luZShkc2kpOwo+ID4gKwkJcmV0dXJuOwo+ID4gKwl9Cj4gPiArCj4gPiArCWRzaS0+aXJxX2Rh
dGEgJj0gfkNNRF9ET05FX0lOVF9GTEFHOwo+IAo+IEkgdGhpbmsgeW91IHNob3VsZCBtb3ZlIHRo
aXMgYmVmb3JlIHRyaWdnZXIgSFcuIFNvbWV0aW1lcyB0aGlzIGludGVycnVwdAo+IGlzIGNvbWlu
ZyBhbmQgdGhpcyBmbGFnIGlzIHNldCBidXQgeW91IGRvIG5vdCB3YWl0IHRoaXMgZXZlbnQgYW5k
IGRvIG5vdAo+IGNsZWFyIGl0LiBUaGVuIHdoZW4geW91IHdhbnQgdG8gd2FpdCwgdGhlIGZsYWcg
aXMgYWxyZWFkeSBzZXQgYnkgbG9uZwo+IHRpbWUgYWdvIGludGVycnVwdC4KT0ssIHdlIHdpbGwg
Zml4IGl0LgoKPiAKPiA+ICt9Cj4gPiArCj4gPiArc3RhdGljIHNzaXplX3QgbXRrX2RzaV9ob3N0
X3JlYWRfY21kKHN0cnVjdCBtdGtfZHNpICpkc2ksCj4gPiArCQkJCSAgICAgY29uc3Qgc3RydWN0
IG1pcGlfZHNpX21zZyAqbXNnKQo+ID4gK3sKPiA+ICsJdTggbWF4X3RyeV9jb3VudCA9IDU7Cj4g
PiArCXUzMiByZWN2X2NudCwgdG1wX3ZhbDsKPiA+ICsJc3RydWN0IGRzaV9yeHR4X2RhdGEgcmVh
ZF9kYXRhMCwgcmVhZF9kYXRhMSwgcmVhZF9kYXRhMiwgcmVhZF9kYXRhMzsKPiA+ICsJdTggY29u
ZmlnLCB0eXBlLCBkYXRhMCwgZGF0YTE7Cj4gPiArCXMzMiByZXQ7Cj4gPiArCj4gPiArCXU4ICpi
dWZmZXIgPSBtc2ctPnJ4X2J1ZjsKPiA+ICsJdTggYnVmZmVyX3NpemUgPSBtc2ctPnJ4X2xlbjsK
PiA+ICsKPiA+ICsJaWYgKHJlYWRsKGRzaS0+cmVncyArIERTSV9NT0RFX0NUUkwpICYgMHgwMykg
ewo+ID4gKwkJZGV2X2luZm8oZHNpLT5kZXYsICJkc2kgZW5naW5lIGlzIG5vdCBjb21tYW5kIG1v
ZGVcbiIpOwo+ID4gKwkJcmV0dXJuIC0xOwo+ID4gKwl9Cj4gPiArCj4gPiArCWlmICghYnVmZmVy
KSB7Cj4gPiArCQlkZXZfaW5mbyhkc2ktPmRldiwgImRzaSByZWNlaXZlIGJ1ZmZlciBzaXplIG1h
eSBiZSBOVUxMXG4iKTsKPiA+ICsJCXJldHVybiAtMTsKPiA+ICsJfQo+ID4gKwo+ID4gKwlkbyB7
Cj4gPiArCQlpZiAobWF4X3RyeV9jb3VudCA9PSAwKSB7Cj4gPiArCQkJZGV2X2luZm8oZHNpLT5k
ZXYsICJkc2kgZW5naW5lIHJlYWQgY291bnRlciBoYXMgYmVlbiBtYXhpbnVtXG4iKTsKPiA+ICsJ
CQlyZXR1cm4gLTE7Cj4gPiArCQl9Cj4gPiArCj4gPiArCQltYXhfdHJ5X2NvdW50LS07Cj4gPiAr
CQlyZWN2X2NudCA9IDA7Cj4gPiArCj4gPiArCQltdGtfZHNpX3dhaXRfZm9yX2lkbGUoZHNpKTsK
PiA+ICsKPiA+ICsJCWNvbmZpZyA9IDB4MDQ7Cj4gPiArCQlkYXRhMCA9ICooKHU4ICopKG1zZy0+
dHhfYnVmKSk7Cj4gPiArCj4gPiArCQlpZiAoYnVmZmVyX3NpemUgPCAzKQo+ID4gKwkJCXR5cGUg
PSBNSVBJX0RTSV9EQ1NfUkVBRDsKPiA+ICsJCWVsc2UKPiA+ICsJCQl0eXBlID0gTUlQSV9EU0lf
R0VORVJJQ19SRUFEX1JFUVVFU1RfMV9QQVJBTTsKPiA+ICsKPiA+ICsJCWRhdGExID0gMDsKPiA+
ICsKPiA+ICsJCXRtcF92YWwgPSAoZGF0YTEgPDwgMjQpIHwgKGRhdGEwIDw8IDE2KSB8ICh0eXBl
IDw8IDgpIHwgY29uZmlnOwo+ID4gKwo+ID4gKwkJd3JpdGVsKHRtcF92YWwsIGRzaS0+cmVncyAr
IERTSV9DTURRMCk7Cj4gPiArCQltdGtfZHNpX21hc2soZHNpLCBEU0lfQ01EUV9TSVpFLCBDTURR
X1NJWkUsIDEpOwo+ID4gKwo+ID4gKwkJbXRrX2RzaV9zdGFydChkc2kpOwo+IAo+IFRoaXMgcGFy
dCBsb29rcyBsaWtlIHRoZSBzYW1lIGFzIG10a19kc2lfaG9zdF93cml0ZV9jbWQoKSB3aXRoCj4g
bXNnLT50eF9sZW4gPSAxLiBNYXliZSB5b3UgY2FuIHRyeSB0byBtZXJnZSB0aGVzZSB0d28gcGFy
dC4KV2lsbCBkby4KCj4gCj4gPiArCj4gPiArCQkvKiAycyB0aW1lb3V0Ki8KPiA+ICsJCXJldCA9
IHdhaXRfZXZlbnRfaW50ZXJydXB0aWJsZV90aW1lb3V0KF9kc2lfZGNzX3JlYWRfd2FpdF9xdWV1
ZSwKPiA+ICsJCQkJZHNpLT5pcnFfZGF0YSAmIExQUlhfUkRfUkRZX0lOVF9GTEFHLCB0aW1lb3V0
KTsKPiA+ICsJCWlmIChyZXQgPT0gMCkgewo+ID4gKwkJCWRldl9pbmZvKGRzaS0+ZGV2LCAiV2Fp
dCBEU0kgcmVhZCByZWFkeSB0aW1lb3V0ISEhXG4iKTsKPiA+ICsKPiA+ICsJCQltdGtfZHNpX2Vu
YWJsZShkc2kpOwo+ID4gKwkJCW10a19kc2lfcmVzZXRfZW5naW5lKGRzaSk7Cj4gPiArCj4gPiAr
CQkJcmV0dXJuIHJldDsKPiA+ICsJCX0KPiA+ICsKPiA+ICsJCWRzaS0+aXJxX2RhdGEgJj0gfkxQ
UlhfUkRfUkRZX0lOVF9GTEFHOwo+IAo+IEkgdGhpbmsgeW91IHNob3VsZCBtb3ZlIHRoaXMgYmVm
b3JlIHRyaWdnZXIgSFcuIFNvbWV0aW1lcyB0aGlzIGludGVycnVwdAo+IGlzIGNvbWluZyBhbmQg
dGhpcyBmbGFnIGlzIHNldCBidXQgeW91IGRvIG5vdCB3YWl0IHRoaXMgZXZlbnQgYW5kIGRvIG5v
dAo+IGNsZWFyIGl0LiBUaGVuIHdoZW4geW91IHdhbnQgdG8gd2FpdCwgdGhlIGZsYWcgaXMgYWxy
ZWFkeSBzZXQgYnkgbG9uZwo+IHRpbWUgYWdvIGludGVycnVwdC4KV2lsbCBkby4KCj4gCj4gPiAr
Cj4gPiArCQkqKHUzMiAqKSgmcmVhZF9kYXRhMCkgPSByZWFkbChkc2ktPnJlZ3MgKyBEU0lfUlhf
REFUQTApOwo+ID4gKwkJKih1MzIgKikoJnJlYWRfZGF0YTEpID0gcmVhZGwoZHNpLT5yZWdzICsg
RFNJX1JYX0RBVEExKTsKPiA+ICsJCSoodTMyICopKCZyZWFkX2RhdGEyKSA9IHJlYWRsKGRzaS0+
cmVncyArIERTSV9SWF9EQVRBMik7Cj4gPiArCQkqKHUzMiAqKSgmcmVhZF9kYXRhMykgPSByZWFk
bChkc2ktPnJlZ3MgKyBEU0lfUlhfREFUQTMpOwo+ID4gKwo+ID4gKwkJdHlwZSA9IHJlYWRfZGF0
YTAuYnl0ZTA7Cj4gPiArCj4gPiArCQlpZiAodHlwZSA9PSBNSVBJX0RTSV9SWF9HRU5FUklDX0xP
TkdfUkVBRF9SRVNQT05TRSB8fAo+ID4gKwkJICAgIHR5cGUgPT0gTUlQSV9EU0lfUlhfRENTX0xP
TkdfUkVBRF9SRVNQT05TRSkgewo+ID4gKwo+ID4gKwkJCS8qCj4gPiArCQkJICogRGF0YSBJRCgx
IGJ5dGUpICsgV29yZCBDb3VudCgyIGJ5dGVzKSArIEVDQygxIGJ5dGUpICsKPiA+ICsJCQkgKiBk
YXRhIDAgKyAuLi4rIGRhdGEgV0MtMSArIENIRUNLU1VNICgyIGJ5dGVzKQo+IAo+IElzIENIRUNL
U1VNIHVzZWxlc3M/IFdoeSBub3QgY2hlY2sgaXQ/CldlIHdpbGwgY2hlY2sgdGhpcy4KCj4gCj4g
PiArCQkJICovCj4gPiArCQkJcmVjdl9jbnQgPSByZWFkX2RhdGEwLmJ5dGUxICsgcmVhZF9kYXRh
MC5ieXRlMiAqIDE2Owo+ID4gKwkJCWRldl9pbmZvKGRzaS0+ZGV2LCAibG9uZyBwYWNrZXQgc2l6
ZTogJWRcbiIsIHJlY3ZfY250KTsKPiA+ICsKPiA+ICsJCQkvKgo+ID4gKwkJCSAqIHRoZSBidWZm
ZXIgc2l6ZSBpcyAxNiBieXRlcyBvbmNlLCBzbyB0aGUgZGF0YSBwYXlsb2FkCj4gPiArCQkJICog
aXMsIDE2IC0gYnl0ZXMoZGF0YSBJRCArIFdDICsgRUNDICsgQ0hFQ0tTVU0pLCBpZgo+ID4gKwkJ
CSAqIG92ZXIgMTAgYnl0ZXMsIGl0IHdpbGwgYmUgcmVhZCBhZ2Fpbgo+ID4gKwkJCSAqLwo+ID4g
KwkJCWlmIChyZWN2X2NudCA+IDEwKQo+ID4gKwkJCQlyZWN2X2NudCA9IDEwOwo+ID4gKwo+ID4g
KwkJCWlmIChyZWN2X2NudCA+IGJ1ZmZlcl9zaXplKQo+ID4gKwkJCQlyZWN2X2NudCA9IGJ1ZmZl
cl9zaXplOwo+ID4gKwo+ID4gKwkJCWlmIChyZWN2X2NudCA8PSA0KSB7Cj4gPiArCQkJCW1lbWNw
eShidWZmZXIsICZyZWFkX2RhdGExLCByZWN2X2NudCk7Cj4gPiArCQkJfSBlbHNlIGlmIChyZWN2
X2NudCA8PSA4KSB7Cj4gPiArCQkJCW1lbWNweShidWZmZXIsICZyZWFkX2RhdGExLCA0KTsKPiA+
ICsJCQkJbWVtY3B5KGJ1ZmZlciArIDQsICZyZWFkX2RhdGEyLCByZWN2X2NudCAtIDQpOwo+ID4g
KwkJCX0gZWxzZSB7Cj4gPiArCQkJCW1lbWNweShidWZmZXIsICZyZWFkX2RhdGExLCA0KTsKPiA+
ICsJCQkJbWVtY3B5KGJ1ZmZlciArIDQsICZyZWFkX2RhdGEyLCA0KTsKPiA+ICsJCQkJbWVtY3B5
KGJ1ZmZlciArIDgsICZyZWFkX2RhdGEzLCByZWN2X2NudCAtIDgpOwo+ID4gKwkJCX0KPiAKPiBJ
IHRoaW5rIHlvdSBjYW4gaWdub3JlIHJlYWRfZGF0YTEsIHJlYWRfZGF0YTIsIGFuZCByZWFkX2Rh
dGEzLiBVc2luZyBhCj4gJ2ZvciBsb29wJyBhbmQgcmVhZGIoKSBoZXJlIGNhbiBkaXJlY3RseSBy
ZWFkIHJlZ2lzdGVyIGRhdGEgaW50byBidWZmZXIuCldlIHdpbGwgcmV3cml0ZSB0aGlzIHBhcnQu
Cgo+IAo+IAo+ID4gKwkJfSBlbHNlIGlmICh0eXBlID09IE1JUElfRFNJX1JYX0dFTkVSSUNfU0hP
UlRfUkVBRF9SRVNQT05TRV8xQllURSB8fAo+ID4gKwkJCSAgIHR5cGUgPT0gTUlQSV9EU0lfUlhf
R0VORVJJQ19TSE9SVF9SRUFEX1JFU1BPTlNFXzJCWVRFIHx8Cj4gPiArCQkJICAgdHlwZSA9PSBN
SVBJX0RTSV9SWF9EQ1NfU0hPUlRfUkVBRF9SRVNQT05TRV8xQllURSB8fAo+ID4gKwkJCSAgIHR5
cGUgPT0gTUlQSV9EU0lfUlhfRENTX1NIT1JUX1JFQURfUkVTUE9OU0VfMkJZVEUpIHsKPiA+ICsK
PiA+ICsJCQlpZiAodHlwZSA9PSBNSVBJX0RTSV9SWF9HRU5FUklDX1NIT1JUX1JFQURfUkVTUE9O
U0VfMUJZVEUgfHwKPiA+ICsJCQkgICAgdHlwZSA9PSBNSVBJX0RTSV9SWF9EQ1NfU0hPUlRfUkVB
RF9SRVNQT05TRV8xQllURSkKPiA+ICsJCQkJcmVjdl9jbnQgPSAxOwo+ID4gKwkJCWVsc2UKPiA+
ICsJCQkJcmVjdl9jbnQgPSAyOwo+ID4gKwo+ID4gKwkJCWlmIChyZWN2X2NudCA+IGJ1ZmZlcl9z
aXplKQo+ID4gKwkJCQlyZWN2X2NudCA9IGJ1ZmZlcl9zaXplOwo+ID4gKwo+ID4gKwkJCW1lbWNw
eShidWZmZXIsICZyZWFkX2RhdGEwLmJ5dGUxLCByZWN2X2NudCk7Cj4gPiArCQl9IGVsc2UgaWYg
KHR5cGUgPT0gTUlQSV9EU0lfUlhfQUNLTk9XTEVER0VfQU5EX0VSUk9SX1JFUE9SVCkgewo+ID4g
KwkJCWRldl9pbmZvKGRzaS0+ZGV2LCAicGFja2V0IHR5cGUgaXMgMHgwMiwgdHJ5IGFnYWluXG4i
KTsKPiA+ICsJCX0gZWxzZSB7Cj4gPiArCQkJZGV2X2luZm8oZHNpLT5kZXYsICJwYWNrZXQgdHlw
ZSgweCV4KSBjYW5ub3QgYmUgbm9uLXJlY29nbml6ZVxuIiwKPiA+ICsJCQkJIHR5cGUpOwo+ID4g
Kwo+ID4gKwkJCXJldHVybiAwOwo+ID4gKwkJfQo+ID4gKwl9IHdoaWxlICh0eXBlID09IE1JUElf
RFNJX1JYX0FDS05PV0xFREdFX0FORF9FUlJPUl9SRVBPUlQpOwo+ID4gKwo+ID4gKwlkZXZfaW5m
byhkc2ktPmRldiwgImRzaSBnZXQgJWQgYnl0ZSBkYXRhIGZyb20gdGhlIHBhbmVsIGFkZHJlc3Mo
MHgleClcbiIsCj4gPiArCQkgcmVjdl9jbnQsICooKHU4ICopKG1zZy0+dHhfYnVmKSkpOwo+ID4g
Kwo+ID4gKwlyZXR1cm4gcmVjdl9jbnQ7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBzc2l6ZV90
IG10a19kc2lfaG9zdF93cml0ZV9jbWQoc3RydWN0IG10a19kc2kgKmRzaSwKPiA+ICsJCQkJICAg
ICAgY29uc3Qgc3RydWN0IG1pcGlfZHNpX21zZyAqbXNnKQo+ID4gK3sKPiA+ICsJdTMyIGk7Cj4g
PiArCXUzMiBnb3RvX2FkZHIsIG1hc2tfcGFyYSwgc2V0X3BhcmEsIHJlZ192YWw7Cj4gPiArCXZv
aWQgX19pb21lbSAqY21kcV9yZWc7Cj4gPiArCXU4IGNvbmZpZywgdHlwZSwgZGF0YTAsIGRhdGEx
Owo+ID4gKwl1MTYgd2MxNjsKPiA+ICsJY29uc3QgY2hhciAqdHhfYnVmID0gbXNnLT50eF9idWY7
Cj4gPiArCXN0cnVjdCBkc2lfdHhfY21kcV9yZWdzICpkc2lfY21kX3JlZzsKPiA+ICsKPiA+ICsJ
ZHNpX2NtZF9yZWcgPSAoc3RydWN0IGRzaV90eF9jbWRxX3JlZ3MgKikoZHNpLT5yZWdzICsgRFNJ
X0NNRFEwKTsKPiA+ICsKPiA+ICsJbXRrX2RzaV93YWl0X2Zvcl9pZGxlKGRzaSk7Cj4gPiArCj4g
PiArCWlmIChtc2ctPnR4X2xlbiA+IDIpIHsKPiA+ICsJCWNvbmZpZyA9IDI7Cj4gPiArCQl0eXBl
ID0gbXNnLT50eXBlOwo+ID4gKwkJd2MxNiA9IG1zZy0+dHhfbGVuOwo+ID4gKwo+ID4gKwkJcmVn
X3ZhbCA9ICh3YzE2IDw8IDE2KSB8ICh0eXBlIDw8IDgpIHwgY29uZmlnOwo+ID4gKwo+ID4gKwkJ
d3JpdGVsKHJlZ192YWwsICZkc2lfY21kX3JlZy0+ZGF0YVswXSk7Cj4gPiArCj4gPiArCQlmb3Ig
KGkgPSAwOyBpIDwgbXNnLT50eF9sZW47IGkrKykgewo+ID4gKwkJCWdvdG9fYWRkciA9ICh1MzIp
KCZkc2lfY21kX3JlZy0+ZGF0YVsxXS5ieXRlMCkgKyBpOwo+ID4gKwkJCW1hc2tfcGFyYSA9ICgw
eGZmIDw8ICgoZ290b19hZGRyICYgMHgzKSAqIDgpKTsKPiA+ICsJCQlzZXRfcGFyYSA9ICh0eF9i
dWZbaV0gPDwgKChnb3RvX2FkZHIgJiAweDMpICogOCkpOwo+ID4gKwkJCWNtZHFfcmVnID0gKHZv
aWQgX19pb21lbSAqKShnb3RvX2FkZHIgJiAofjB4MykpOwo+ID4gKwkJCW10a19kc2lfc2V0X2Nt
ZHEoY21kcV9yZWcsIG1hc2tfcGFyYSwgc2V0X3BhcmEpOwo+ID4gKwkJfQo+IAo+IEJlY2F1c2Ug
eW91IHVzZSB3cml0ZWwoKSwgc28gdGhpcyBwYXJ0IGxvb2sgc28gY29tcGxpY2F0ZWQuIElmIHlv
dSB1c2UKPiB3cml0ZWIoKSwgdGhpcyB3b3VsZCBiZSBtdWNoIHNpbXBsZXIuCk9LLCB3ZSB3aWxs
IHVzZSB3cml0ZWIoKSBpbiB0aGUgbmV4dCB2ZXJzaW9uLgoKUmVnYXJkcywKeXQuc2hlbgoKPiAK
PiA+ICsKPiA+ICsJCW10a19kc2lfbWFzayhkc2ksIERTSV9DTURRX1NJWkUsIENNRFFfU0laRSwK
PiA+ICsJCQkgICAgIDEgKyAobXNnLT50eF9sZW4gKyAzKSAvIDQpOwo+ID4gKwl9IGVsc2Ugewo+
ID4gKwkJY29uZmlnID0gMDsKPiA+ICsJCWRhdGEwID0gdHhfYnVmWzBdOwo+ID4gKwkJaWYgKG1z
Zy0+dHhfbGVuID09IDIpIHsKPiA+ICsJCQl0eXBlID0gTUlQSV9EU0lfRENTX1NIT1JUX1dSSVRF
X1BBUkFNOwo+ID4gKwkJCWRhdGExID0gdHhfYnVmWzFdOwo+ID4gKwkJfSBlbHNlIHsKPiA+ICsJ
CQl0eXBlID0gTUlQSV9EU0lfRENTX1NIT1JUX1dSSVRFOwo+ID4gKwkJCWRhdGExID0gMDsKPiA+
ICsJCX0KPiA+ICsKPiA+ICsJCXJlZ192YWwgPSAoZGF0YTEgPDwgMjQpIHwgKGRhdGEwIDw8IDE2
KSB8ICh0eXBlIDw8IDgpIHwgY29uZmlnOwo+ID4gKwo+ID4gKwkJd3JpdGVsKHJlZ192YWwsICZk
c2lfY21kX3JlZy0+ZGF0YVswXSk7Cj4gPiArCQltdGtfZHNpX21hc2soZHNpLCBEU0lfQ01EUV9T
SVpFLCBDTURRX1NJWkUsIDEpOwo+ID4gKwl9Cj4gPiArCj4gPiArCW10a19kc2lfc3RhcnQoZHNp
KTsKPiA+ICsJbXRrX2RzaV93YWl0X2Zvcl9jbWRfZG9uZShkc2kpOwo+ID4gKwo+ID4gKwlyZXR1
cm4gMDsKPiA+ICt9Cj4gPiArCj4gPiArc3RhdGljIHNzaXplX3QgbXRrX2RzaV9ob3N0X3RyYW5z
ZmVyKHN0cnVjdCBtaXBpX2RzaV9ob3N0ICpob3N0LAo+ID4gKwkJCQkgICAgIGNvbnN0IHN0cnVj
dCBtaXBpX2RzaV9tc2cgKm1zZykKPiA+ICt7Cj4gPiArCXN0cnVjdCBtdGtfZHNpICpkc2kgPSBo
b3N0X3RvX2RzaShob3N0KTsKPiA+ICsJdTggdHlwZSA9IG1zZy0+dHlwZTsKPiA+ICsJc3NpemVf
dCByZXQgPSAwOwo+ID4gKwo+ID4gKwlpZiAoTVRLX0RTSV9IT1NUX0lTX1JFQUQodHlwZSkpCj4g
PiArCQlyZXQgPSBtdGtfZHNpX2hvc3RfcmVhZF9jbWQoZHNpLCBtc2cpOwo+ID4gKwllbHNlIGlm
IChNVEtfRFNJX0hPU1RfSVNfV1JJVEUodHlwZSkpCj4gPiArCQlyZXQgPSBtdGtfZHNpX2hvc3Rf
d3JpdGVfY21kKGRzaSwgbXNnKTsKPiA+ICsKPiA+ICsJcmV0dXJuIHJldDsKPiA+ICt9Cj4gPiAr
Cj4gPiAgc3RhdGljIGNvbnN0IHN0cnVjdCBtaXBpX2RzaV9ob3N0X29wcyBtdGtfZHNpX29wcyA9
IHsKPiA+ICAJLmF0dGFjaCA9IG10a19kc2lfaG9zdF9hdHRhY2gsCj4gPiAgCS5kZXRhY2ggPSBt
dGtfZHNpX2hvc3RfZGV0YWNoLAo+ID4gKwkudHJhbnNmZXIgPSBtdGtfZHNpX2hvc3RfdHJhbnNm
ZXIsCj4gPiAgfTsKPiA+ICAKPiA+ICBzdGF0aWMgaW50IG10a19kc2lfYmluZChzdHJ1Y3QgZGV2
aWNlICpkZXYsIHN0cnVjdCBkZXZpY2UgKm1hc3Rlciwgdm9pZCAqZGF0YSkKPiAKPiBSZWdhcmRz
LAo+IENLCj4gCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f
X18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3Jn
Cmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVs
Cg==

From mboxrd@z Thu Jan  1 00:00:00 1970
From: yt.shen@mediatek.com (YT Shen)
Date: Tue, 2 Aug 2016 17:14:48 +0800
Subject: [PATCH v5 07/10] drm/mediatek: add dsi transfer function
In-Reply-To: <1470120958.16554.16.camel@mtksdaap41>
References: <1469698084-20185-1-git-send-email-yt.shen@mediatek.com>
 <1469698084-20185-8-git-send-email-yt.shen@mediatek.com>
 <1470120958.16554.16.camel@mtksdaap41>
Message-ID: <1470129288.30671.13.camel@mtksdaap41>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

Hi CK,

On Tue, 2016-08-02 at 14:55 +0800, CK Hu wrote:
> Hi, YT:
> 
> On Thu, 2016-07-28 at 17:28 +0800, YT Shen wrote:
> > From: shaoming chen <shaoming.chen@mediatek.com>
> > 
> > add dsi read/write commands for transfer function
> > 
> > Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_dsi.c |  286 ++++++++++++++++++++++++++++++++++++
> >  1 file changed, 286 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 553443a..1d36524 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -24,6 +24,7 @@
> >  #include <linux/of_graph.h>
> >  #include <linux/phy/phy.h>
> >  #include <linux/platform_device.h>
> > +#include <video/mipi_display.h>
> >  #include <video/videomode.h>
> >  
> >  #include "mtk_drm_ddp_comp.h"
> > @@ -81,8 +82,16 @@
> >  #define DSI_HBP_WC		0x54
> >  #define DSI_HFP_WC		0x58
> >  
> > +#define DSI_CMDQ_SIZE		0x60
> > +#define CMDQ_SIZE		0x3f
> > +
> >  #define DSI_HSTX_CKL_WC		0x64
> >  
> > +#define DSI_RX_DATA0		0x74
> > +#define DSI_RX_DATA1		0x78
> > +#define DSI_RX_DATA2		0x7c
> > +#define DSI_RX_DATA3		0x80
> > +
> >  #define DSI_RACK		0x84
> >  #define RACK				BIT(0)
> >  
> > @@ -118,8 +127,25 @@
> >  #define CLK_HS_POST			(0xff << 8)
> >  #define CLK_HS_EXIT			(0xff << 16)
> >  
> > +#define DSI_CMDQ0		0x180
> > +
> >  #define NS_TO_CYCLE(n, c)    ((n) / (c) + (((n) % (c)) ? 1 : 0))
> >  
> > +#define MTK_DSI_HOST_IS_READ(type) \
> > +	((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
> > +	(type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
> > +	(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
> > +	(type == MIPI_DSI_DCS_READ))
> > +
> > +#define MTK_DSI_HOST_IS_WRITE(type) \
> > +	((type == MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM) || \
> > +	(type == MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM) || \
> > +	(type == MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM) || \
> > +	(type == MIPI_DSI_DCS_SHORT_WRITE) || \
> > +	(type == MIPI_DSI_DCS_SHORT_WRITE_PARAM) || \
> > +	(type == MIPI_DSI_GENERIC_LONG_WRITE) || \
> > +	(type == MIPI_DSI_DCS_LONG_WRITE))
> > +
> >  struct phy;
> >  
> >  struct mtk_dsi {
> > @@ -149,6 +175,17 @@ struct mtk_dsi {
> >  	int irq_data;
> >  };
> >  
> > +struct dsi_rxtx_data {
> > +	u8 byte0;
> > +	u8 byte1;
> > +	u8 byte2;
> > +	u8 byte3;
> > +};
> > +
> > +struct dsi_tx_cmdq_regs {
> > +	struct dsi_rxtx_data data[128];
> > +};
> > +
> >  static wait_queue_head_t _dsi_cmd_done_wait_queue;
> >  static wait_queue_head_t _dsi_dcs_read_wait_queue;
> >  static wait_queue_head_t _dsi_wait_vm_done_queue;
> > @@ -813,9 +850,258 @@ static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
> >  	return 0;
> >  }
> >  
> > +static void mtk_dsi_set_cmdq(void __iomem *reg, u32 mask, u32 data)
> > +{
> > +	u32 temp = readl(reg);
> > +
> > +	writel((temp & ~mask) | (data & mask), reg);
> > +}
> > +
> > +static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
> > +{
> > +	u32 timeout_ms = 500000; /* total 1s ~ 2s timeout */
> > +
> > +	while (timeout_ms--) {
> > +		if (!(readl(dsi->regs + DSI_INTSTA) & DSI_BUSY))
> > +			break;
> > +
> > +		usleep_range(2, 4);
> > +	}
> > +
> > +	if (timeout_ms == 0) {
> > +		dev_info(dsi->dev, "polling dsi wait not busy timeout!\n");
> > +
> > +		mtk_dsi_enable(dsi);
> > +		mtk_dsi_reset_engine(dsi);
> > +	}
> > +}
> > +
> > +static void mtk_dsi_wait_for_cmd_done(struct mtk_dsi *dsi)
> > +{
> > +	s32 ret = 0;
> > +	unsigned long timeout = msecs_to_jiffies(500);
> > +
> > +	ret = wait_event_interruptible_timeout(_dsi_cmd_done_wait_queue,
> > +			dsi->irq_data & CMD_DONE_INT_FLAG, timeout);
> > +	if (ret == 0) {
> > +		dev_info(dsi->dev, "dsi wait engine cmd done fail\n");
> > +		mtk_dsi_enable(dsi);
> > +		mtk_dsi_reset_engine(dsi);
> > +		return;
> > +	}
> > +
> > +	dsi->irq_data &= ~CMD_DONE_INT_FLAG;
> 
> I think you should move this before trigger HW. Sometimes this interrupt
> is coming and this flag is set but you do not wait this event and do not
> clear it. Then when you want to wait, the flag is already set by long
> time ago interrupt.
OK, we will fix it.

> 
> > +}
> > +
> > +static ssize_t mtk_dsi_host_read_cmd(struct mtk_dsi *dsi,
> > +				     const struct mipi_dsi_msg *msg)
> > +{
> > +	u8 max_try_count = 5;
> > +	u32 recv_cnt, tmp_val;
> > +	struct dsi_rxtx_data read_data0, read_data1, read_data2, read_data3;
> > +	u8 config, type, data0, data1;
> > +	s32 ret;
> > +
> > +	u8 *buffer = msg->rx_buf;
> > +	u8 buffer_size = msg->rx_len;
> > +
> > +	if (readl(dsi->regs + DSI_MODE_CTRL) & 0x03) {
> > +		dev_info(dsi->dev, "dsi engine is not command mode\n");
> > +		return -1;
> > +	}
> > +
> > +	if (!buffer) {
> > +		dev_info(dsi->dev, "dsi receive buffer size may be NULL\n");
> > +		return -1;
> > +	}
> > +
> > +	do {
> > +		if (max_try_count == 0) {
> > +			dev_info(dsi->dev, "dsi engine read counter has been maxinum\n");
> > +			return -1;
> > +		}
> > +
> > +		max_try_count--;
> > +		recv_cnt = 0;
> > +
> > +		mtk_dsi_wait_for_idle(dsi);
> > +
> > +		config = 0x04;
> > +		data0 = *((u8 *)(msg->tx_buf));
> > +
> > +		if (buffer_size < 3)
> > +			type = MIPI_DSI_DCS_READ;
> > +		else
> > +			type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
> > +
> > +		data1 = 0;
> > +
> > +		tmp_val = (data1 << 24) | (data0 << 16) | (type << 8) | config;
> > +
> > +		writel(tmp_val, dsi->regs + DSI_CMDQ0);
> > +		mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, 1);
> > +
> > +		mtk_dsi_start(dsi);
> 
> This part looks like the same as mtk_dsi_host_write_cmd() with
> msg->tx_len = 1. Maybe you can try to merge these two part.
Will do.

> 
> > +
> > +		/* 2s timeout*/
> > +		ret = wait_event_interruptible_timeout(_dsi_dcs_read_wait_queue,
> > +				dsi->irq_data & LPRX_RD_RDY_INT_FLAG, timeout);
> > +		if (ret == 0) {
> > +			dev_info(dsi->dev, "Wait DSI read ready timeout!!!\n");
> > +
> > +			mtk_dsi_enable(dsi);
> > +			mtk_dsi_reset_engine(dsi);
> > +
> > +			return ret;
> > +		}
> > +
> > +		dsi->irq_data &= ~LPRX_RD_RDY_INT_FLAG;
> 
> I think you should move this before trigger HW. Sometimes this interrupt
> is coming and this flag is set but you do not wait this event and do not
> clear it. Then when you want to wait, the flag is already set by long
> time ago interrupt.
Will do.

> 
> > +
> > +		*(u32 *)(&read_data0) = readl(dsi->regs + DSI_RX_DATA0);
> > +		*(u32 *)(&read_data1) = readl(dsi->regs + DSI_RX_DATA1);
> > +		*(u32 *)(&read_data2) = readl(dsi->regs + DSI_RX_DATA2);
> > +		*(u32 *)(&read_data3) = readl(dsi->regs + DSI_RX_DATA3);
> > +
> > +		type = read_data0.byte0;
> > +
> > +		if (type == MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE ||
> > +		    type == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
> > +
> > +			/*
> > +			 * Data ID(1 byte) + Word Count(2 bytes) + ECC(1 byte) +
> > +			 * data 0 + ...+ data WC-1 + CHECKSUM (2 bytes)
> 
> Is CHECKSUM useless? Why not check it?
We will check this.

> 
> > +			 */
> > +			recv_cnt = read_data0.byte1 + read_data0.byte2 * 16;
> > +			dev_info(dsi->dev, "long packet size: %d\n", recv_cnt);
> > +
> > +			/*
> > +			 * the buffer size is 16 bytes once, so the data payload
> > +			 * is, 16 - bytes(data ID + WC + ECC + CHECKSUM), if
> > +			 * over 10 bytes, it will be read again
> > +			 */
> > +			if (recv_cnt > 10)
> > +				recv_cnt = 10;
> > +
> > +			if (recv_cnt > buffer_size)
> > +				recv_cnt = buffer_size;
> > +
> > +			if (recv_cnt <= 4) {
> > +				memcpy(buffer, &read_data1, recv_cnt);
> > +			} else if (recv_cnt <= 8) {
> > +				memcpy(buffer, &read_data1, 4);
> > +				memcpy(buffer + 4, &read_data2, recv_cnt - 4);
> > +			} else {
> > +				memcpy(buffer, &read_data1, 4);
> > +				memcpy(buffer + 4, &read_data2, 4);
> > +				memcpy(buffer + 8, &read_data3, recv_cnt - 8);
> > +			}
> 
> I think you can ignore read_data1, read_data2, and read_data3. Using a
> 'for loop' and readb() here can directly read register data into buffer.
We will rewrite this part.

> 
> 
> > +		} else if (type == MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE ||
> > +			   type == MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE ||
> > +			   type == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE ||
> > +			   type == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
> > +
> > +			if (type == MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE ||
> > +			    type == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)
> > +				recv_cnt = 1;
> > +			else
> > +				recv_cnt = 2;
> > +
> > +			if (recv_cnt > buffer_size)
> > +				recv_cnt = buffer_size;
> > +
> > +			memcpy(buffer, &read_data0.byte1, recv_cnt);
> > +		} else if (type == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
> > +			dev_info(dsi->dev, "packet type is 0x02, try again\n");
> > +		} else {
> > +			dev_info(dsi->dev, "packet type(0x%x) cannot be non-recognize\n",
> > +				 type);
> > +
> > +			return 0;
> > +		}
> > +	} while (type == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT);
> > +
> > +	dev_info(dsi->dev, "dsi get %d byte data from the panel address(0x%x)\n",
> > +		 recv_cnt, *((u8 *)(msg->tx_buf)));
> > +
> > +	return recv_cnt;
> > +}
> > +
> > +static ssize_t mtk_dsi_host_write_cmd(struct mtk_dsi *dsi,
> > +				      const struct mipi_dsi_msg *msg)
> > +{
> > +	u32 i;
> > +	u32 goto_addr, mask_para, set_para, reg_val;
> > +	void __iomem *cmdq_reg;
> > +	u8 config, type, data0, data1;
> > +	u16 wc16;
> > +	const char *tx_buf = msg->tx_buf;
> > +	struct dsi_tx_cmdq_regs *dsi_cmd_reg;
> > +
> > +	dsi_cmd_reg = (struct dsi_tx_cmdq_regs *)(dsi->regs + DSI_CMDQ0);
> > +
> > +	mtk_dsi_wait_for_idle(dsi);
> > +
> > +	if (msg->tx_len > 2) {
> > +		config = 2;
> > +		type = msg->type;
> > +		wc16 = msg->tx_len;
> > +
> > +		reg_val = (wc16 << 16) | (type << 8) | config;
> > +
> > +		writel(reg_val, &dsi_cmd_reg->data[0]);
> > +
> > +		for (i = 0; i < msg->tx_len; i++) {
> > +			goto_addr = (u32)(&dsi_cmd_reg->data[1].byte0) + i;
> > +			mask_para = (0xff << ((goto_addr & 0x3) * 8));
> > +			set_para = (tx_buf[i] << ((goto_addr & 0x3) * 8));
> > +			cmdq_reg = (void __iomem *)(goto_addr & (~0x3));
> > +			mtk_dsi_set_cmdq(cmdq_reg, mask_para, set_para);
> > +		}
> 
> Because you use writel(), so this part look so complicated. If you use
> writeb(), this would be much simpler.
OK, we will use writeb() in the next version.

Regards,
yt.shen

> 
> > +
> > +		mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE,
> > +			     1 + (msg->tx_len + 3) / 4);
> > +	} else {
> > +		config = 0;
> > +		data0 = tx_buf[0];
> > +		if (msg->tx_len == 2) {
> > +			type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
> > +			data1 = tx_buf[1];
> > +		} else {
> > +			type = MIPI_DSI_DCS_SHORT_WRITE;
> > +			data1 = 0;
> > +		}
> > +
> > +		reg_val = (data1 << 24) | (data0 << 16) | (type << 8) | config;
> > +
> > +		writel(reg_val, &dsi_cmd_reg->data[0]);
> > +		mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, 1);
> > +	}
> > +
> > +	mtk_dsi_start(dsi);
> > +	mtk_dsi_wait_for_cmd_done(dsi);
> > +
> > +	return 0;
> > +}
> > +
> > +static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
> > +				     const struct mipi_dsi_msg *msg)
> > +{
> > +	struct mtk_dsi *dsi = host_to_dsi(host);
> > +	u8 type = msg->type;
> > +	ssize_t ret = 0;
> > +
> > +	if (MTK_DSI_HOST_IS_READ(type))
> > +		ret = mtk_dsi_host_read_cmd(dsi, msg);
> > +	else if (MTK_DSI_HOST_IS_WRITE(type))
> > +		ret = mtk_dsi_host_write_cmd(dsi, msg);
> > +
> > +	return ret;
> > +}
> > +
> >  static const struct mipi_dsi_host_ops mtk_dsi_ops = {
> >  	.attach = mtk_dsi_host_attach,
> >  	.detach = mtk_dsi_host_detach,
> > +	.transfer = mtk_dsi_host_transfer,
> >  };
> >  
> >  static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
> 
> Regards,
> CK
>