From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965255AbcHBMrh (ORCPT ); Tue, 2 Aug 2016 08:47:37 -0400 Received: from mail-pa0-f68.google.com ([209.85.220.68]:36532 "EHLO mail-pa0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965341AbcHBMpz (ORCPT ); Tue, 2 Aug 2016 08:45:55 -0400 From: Chris Zhong To: dianders@chromium.org, tfiga@chromium.org, heiko@sntech.de, yzq@rock-chips.com, groeck@chromium.org, myungjoo.ham@samsung.com, cw00.choi@samsung.com, wulf@rock-chips.com, marcheu@chromium.org Cc: linux-rockchip@lists.infradead.org, Chris Zhong , Mark Yao , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [v9 PATCH 5/6] Documentation: bindings: add dt documentation for cdn DP controller Date: Tue, 2 Aug 2016 20:45:12 +0800 Message-Id: <1470141913-1082-6-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.3 In-Reply-To: <1470141913-1082-1-git-send-email-zyw@rock-chips.com> References: <1470141913-1082-1-git-send-email-zyw@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v9: - modify the reference phy = <&tcphy0 0>, <&tcphy1 0>; Changes in v8: None Changes in v7: None Changes in v6: - add assigned-clocks and assigned-clock-rates - add power-domains Changes in v5: None Changes in v4: - add a reset node - support 2 phys Changes in v3: - add SoC specific compatible string - remove reg = <1>; Changes in v2: None Changes in v1: - add extcon node description - add #sound-dai-cells description .../bindings/display/rockchip/cdn-dp-rockchip.txt | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt new file mode 100644 index 0000000..5ff982a --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt @@ -0,0 +1,74 @@ +Rockchip RK3399 specific extensions to the cdn Display Port +================================ + +Required properties: +- compatible: must be "rockchip,rk3399-cdn-dp" + +- reg: physical base address of the controller and length + +- clocks: from common clock binding: handle to dp clock. + +- clock-names: from common clock binding: + Required elements: "core-clk" "pclk" "spdif" + +- resets : a list of phandle + reset specifier pairs +- reset-names : string reset name, must be: + "spdif" +- power-domains : power-domain property defined with a phandle + to respective power domain. +- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> +- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 + +- rockchip,grf: this soc should set GRF regs, so need get grf here. + +- ports: contain a port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + contained 2 endpoints, connecting to the output of vop. + +- phys: from general PHY binding: the phandle for the PHY device. + +- extcon: extcon specifier for the Power Delivery + +- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF + +------------------------------------------------------------------------------- + +Example: + cdn_dp: dp@fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + interrupts = ; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, + <&cru SCLK_SPDIF_REC_DPTX>; + clock-names = "core-clk", "pclk", "spdif"; + assigned-clocks = <&cru SCLK_DP_CORE>; + assigned-clock-rates = <100000000>; + power-domains = <&power RK3399_PD_HDCP>; + phys = <&tcphy0 0>, <&tcphy1 0>; + resets = <&cru SRST_DPTX_SPDIF_REC>; + reset-names = "spdif"; + extcon = <&fusb0>, <&fusb1>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp_in: port { + #address-cells = <1>; + #size-cells = <0>; + dp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; + }; + }; -- 2.6.3 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Zhong Subject: [v9 PATCH 5/6] Documentation: bindings: add dt documentation for cdn DP controller Date: Tue, 2 Aug 2016 20:45:12 +0800 Message-ID: <1470141913-1082-6-git-send-email-zyw@rock-chips.com> References: <1470141913-1082-1-git-send-email-zyw@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1470141913-1082-1-git-send-email-zyw@rock-chips.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dianders@chromium.org, tfiga@chromium.org, heiko@sntech.de, yzq@rock-chips.com, groeck@chromium.org, myungjoo.ham@samsung.com, cw00.choi@samsung.com, wulf@rock-chips.com, marcheu@chromium.org Cc: Mark Rutland , devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Rob Herring , Kumar Gala , Chris Zhong , linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org VGhpcyBwYXRjaCBhZGRzIGEgYmluZGluZyB0aGF0IGRlc2NyaWJlcyB0aGUgY2RuIERQIGNvbnRy b2xsZXIgZm9yCnJrMzM5OS4KClNpZ25lZC1vZmYtYnk6IENocmlzIFpob25nIDx6eXdAcm9jay1j aGlwcy5jb20+CkFja2VkLWJ5OiBSb2IgSGVycmluZyA8cm9iaEBrZXJuZWwub3JnPgoKLS0tCgpD aGFuZ2VzIGluIHY5OgotIG1vZGlmeSB0aGUgcmVmZXJlbmNlIHBoeSA9IDwmdGNwaHkwIDA+LCA8 JnRjcGh5MSAwPjsKCkNoYW5nZXMgaW4gdjg6IE5vbmUKQ2hhbmdlcyBpbiB2NzogTm9uZQpDaGFu Z2VzIGluIHY2OgotIGFkZCBhc3NpZ25lZC1jbG9ja3MgYW5kIGFzc2lnbmVkLWNsb2NrLXJhdGVz Ci0gYWRkIHBvd2VyLWRvbWFpbnMKCkNoYW5nZXMgaW4gdjU6IE5vbmUKQ2hhbmdlcyBpbiB2NDoK LSBhZGQgYSByZXNldCBub2RlCi0gc3VwcG9ydCAyIHBoeXMKCkNoYW5nZXMgaW4gdjM6Ci0gYWRk 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CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2 ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9s aXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: zyw@rock-chips.com (Chris Zhong) Date: Tue, 2 Aug 2016 20:45:12 +0800 Subject: [v9 PATCH 5/6] Documentation: bindings: add dt documentation for cdn DP controller In-Reply-To: <1470141913-1082-1-git-send-email-zyw@rock-chips.com> References: <1470141913-1082-1-git-send-email-zyw@rock-chips.com> Message-ID: <1470141913-1082-6-git-send-email-zyw@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch adds a binding that describes the cdn DP controller for rk3399. Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v9: - modify the reference phy = <&tcphy0 0>, <&tcphy1 0>; Changes in v8: None Changes in v7: None Changes in v6: - add assigned-clocks and assigned-clock-rates - add power-domains Changes in v5: None Changes in v4: - add a reset node - support 2 phys Changes in v3: - add SoC specific compatible string - remove reg = <1>; Changes in v2: None Changes in v1: - add extcon node description - add #sound-dai-cells description .../bindings/display/rockchip/cdn-dp-rockchip.txt | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt new file mode 100644 index 0000000..5ff982a --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt @@ -0,0 +1,74 @@ +Rockchip RK3399 specific extensions to the cdn Display Port +================================ + +Required properties: +- compatible: must be "rockchip,rk3399-cdn-dp" + +- reg: physical base address of the controller and length + +- clocks: from common clock binding: handle to dp clock. + +- clock-names: from common clock binding: + Required elements: "core-clk" "pclk" "spdif" + +- resets : a list of phandle + reset specifier pairs +- reset-names : string reset name, must be: + "spdif" +- power-domains : power-domain property defined with a phandle + to respective power domain. +- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> +- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 + +- rockchip,grf: this soc should set GRF regs, so need get grf here. + +- ports: contain a port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + contained 2 endpoints, connecting to the output of vop. + +- phys: from general PHY binding: the phandle for the PHY device. + +- extcon: extcon specifier for the Power Delivery + +- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF + +------------------------------------------------------------------------------- + +Example: + cdn_dp: dp at fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + interrupts = ; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, + <&cru SCLK_SPDIF_REC_DPTX>; + clock-names = "core-clk", "pclk", "spdif"; + assigned-clocks = <&cru SCLK_DP_CORE>; + assigned-clock-rates = <100000000>; + power-domains = <&power RK3399_PD_HDCP>; + phys = <&tcphy0 0>, <&tcphy1 0>; + resets = <&cru SRST_DPTX_SPDIF_REC>; + reset-names = "spdif"; + extcon = <&fusb0>, <&fusb1>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp_in: port { + #address-cells = <1>; + #size-cells = <0>; + dp_in_vopb: endpoint at 0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint at 1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; + }; + }; -- 2.6.3