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From: Peter Antoine <peter.antoine@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Alex Dai <yu.dai@intel.com>
Subject: [PATCH v5 4/6] drm/i915/huc: Add debugfs for HuC loading status check
Date: Fri, 12 Aug 2016 09:09:53 +0100	[thread overview]
Message-ID: <1470989395-32517-5-git-send-email-peter.antoine@intel.com> (raw)
In-Reply-To: <1470989395-32517-1-git-send-email-peter.antoine@intel.com>

Add debugfs entry for HuC loading status check.

v2: rebase on-top of drm-intel-nightly.
v3: rebased again.

Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c4f03ea..205d1ce 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2495,6 +2495,38 @@ static int i915_llc(struct seq_file *m, void *data)
 	return 0;
 }
 
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+	if (!HAS_HUC_UCODE(dev_priv))
+		return 0;
+
+	seq_puts(m, "HuC firmware status:\n");
+	seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
+	seq_printf(m, "\tfetch: %s\n",
+		intel_uc_fw_status_repr(huc_fw->fetch_status));
+	seq_printf(m, "\tload: %s\n",
+		intel_uc_fw_status_repr(huc_fw->load_status));
+	seq_printf(m, "\tversion wanted: %d.%d\n",
+		huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+	seq_printf(m, "\tversion found: %d.%d\n",
+		huc_fw->major_ver_found, huc_fw->minor_ver_found);
+	seq_printf(m, "\theader: offset is %d; size = %d\n",
+		huc_fw->header_offset, huc_fw->header_size);
+	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+		huc_fw->ucode_offset, huc_fw->ucode_size);
+	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+		huc_fw->rsa_offset, huc_fw->rsa_size);
+
+	seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
+
+	return 0;
+}
+
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
 	struct drm_info_node *node = m->private;
@@ -5392,6 +5424,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_info", i915_guc_info, 0},
 	{"i915_guc_load_status", i915_guc_load_status_info, 0},
 	{"i915_guc_log_dump", i915_guc_log_dump, 0},
+	{"i915_huc_load_status", i915_huc_load_status_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_drpc_info", i915_drpc_info, 0},
-- 
1.9.1

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  parent reply	other threads:[~2016-08-12  8:10 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-12  8:09 [PATCH v5 0/6] HuC Loading Patches Peter Antoine
2016-08-12  8:09 ` [PATCH v5 1/6] drm/i915/guc: Make the GuC fw loading helper functions general Peter Antoine
2016-08-12  8:09 ` [PATCH v5 2/6] drm/i915/huc: Unified css_header struct for GuC and HuC Peter Antoine
2016-08-12  8:09 ` [PATCH v5 3/6] drm/i915/huc: Add HuC fw loading support Peter Antoine
2016-08-12  8:09 ` Peter Antoine [this message]
2016-08-12  8:09 ` [PATCH v5 5/6] drm/i915/huc: Support HuC authentication Peter Antoine
2016-08-12  8:09 ` [PATCH v5 6/6] drm/i915/huc: Add BXT HuC Loading Support Peter Antoine
2016-08-12  8:34 ` ✗ Ro.CI.BAT: failure for HuC Loading Patches Patchwork
2016-08-12  9:15   ` Antoine, Peter
2016-08-12 11:07     ` Tvrtko Ursulin

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