From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kever Yang Date: Fri, 12 Aug 2016 17:57:05 +0800 Subject: [U-Boot] [PATCH 2/5] clk: rk3288: add PWM clock get rate In-Reply-To: <1470995239-2477-1-git-send-email-kever.yang@rock-chips.com> References: <1470995239-2477-1-git-send-email-kever.yang@rock-chips.com> Message-ID: <1470995825-2908-1-git-send-email-kever.yang@rock-chips.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de This patch add clk_get_rate for PWM device. Signed-off-by: Kever Yang --- drivers/clk/rockchip/clk_rk3288.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index c07203d..bd71a96 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -695,6 +695,8 @@ static ulong rk3288_clk_get_rate(struct clk *clk) case PCLK_I2C4: case PCLK_I2C5: return gclk_rate; + case PCLK_PWM: + return PD_BUS_PCLK_HZ; default: return -ENOENT; } -- 1.9.1