From mboxrd@z Thu Jan 1 00:00:00 1970 From: Zhihong Wang Subject: [PATCH v2 4/6] vhost: add desc prefetch Date: Thu, 18 Aug 2016 02:33:09 -0400 Message-ID: <1471501991-37257-5-git-send-email-zhihong.wang@intel.com> References: <1471319402-112998-1-git-send-email-zhihong.wang@intel.com> <1471501991-37257-1-git-send-email-zhihong.wang@intel.com> Cc: maxime.coquelin@redhat.com, yuanhan.liu@linux.intel.com, Zhihong Wang To: dev@dpdk.org Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id BD6665AB0 for ; Thu, 18 Aug 2016 15:41:13 +0200 (CEST) In-Reply-To: <1471501991-37257-1-git-send-email-zhihong.wang@intel.com> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds descriptor prefetch to hide cache access latency. Signed-off-by: Zhihong Wang --- lib/librte_vhost/vhost_rxtx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lib/librte_vhost/vhost_rxtx.c b/lib/librte_vhost/vhost_rxtx.c index 939957d..7db83d0 100644 --- a/lib/librte_vhost/vhost_rxtx.c +++ b/lib/librte_vhost/vhost_rxtx.c @@ -131,6 +131,11 @@ loop_check(struct vhost_virtqueue *vq, uint16_t avail_idx, uint32_t pkt_left) if (pkt_left == 0 || avail_idx == vq->last_used_idx) return 1; + /* prefetch the next desc */ + if (pkt_left > 1 && avail_idx != vq->last_used_idx + 1) + rte_prefetch0(&vq->desc[vq->avail->ring[ + (vq->last_used_idx + 1) & (vq->size - 1)]]); + return 0; } -- 2.7.4