From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753135AbcHRIEc (ORCPT ); Thu, 18 Aug 2016 04:04:32 -0400 Received: from mail-dm3nam03on0119.outbound.protection.outlook.com ([104.47.41.119]:17194 "EHLO NAM03-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751255AbcHRIEZ (ORCPT ); Thu, 18 Aug 2016 04:04:25 -0400 X-Greylist: delayed 885 seconds by postgrey-1.27 at vger.kernel.org; Thu, 18 Aug 2016 04:04:24 EDT Authentication-Results: spf=neutral (sender IP is 192.88.168.50) smtp.mailfrom=freescale.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=none action=none header.from=freescale.com;nxp.com; dkim=none (message not signed) header.d=none; From: Yunhui Cui To: , , , CC: , , , , Yunhui Cui Subject: [PATCH v3 4/9] mtd: spi-nor: fsl-quadspi: extend support for some special requerment. Date: Thu, 18 Aug 2016 15:37:59 +0800 Message-ID: <1471505884-33996-4-git-send-email-B56489@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 In-Reply-To: <1471505884-33996-1-git-send-email-B56489@freescale.com> References: <1471505884-33996-1-git-send-email-B56489@freescale.com> X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:192.88.168.50;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(7916002)(2980300002)(189002)(199003)(81166006)(8936002)(189998001)(586003)(105606002)(50226002)(47776003)(229853001)(48376002)(5003940100001)(92566002)(81156014)(36756003)(106466001)(2950100001)(356003)(50466002)(68736007)(8676002)(50986999)(77096005)(4326007)(11100500001)(305945005)(2201001)(97736004)(8666005)(626004)(5001770100001)(87936001)(7846002)(2906002)(76176999)(19580395003)(104016004)(19580405001)(575784001)(7059030);DIR:OUT;SFP:1102;SCL:1;SRVR:CY1PR0301MB2122;H:tx30smr01.am.freescale.net;FPR:;SPF:Neutral;PTR:InfoDomainNonexistent;MX:1;A:1;LANG:en; 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Spansion S25FS-S family flash need some special operations. Signed-off-by: Yunhui Cui --- drivers/mtd/spi-nor/fsl-quadspi.c | 44 +++++++++++++++++++++++++++++++++++++-- include/linux/mtd/spi-nor.h | 4 ++++ 2 files changed, 46 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index b0a74b8..2521370 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -205,6 +205,9 @@ #define SEQID_RDCR 9 #define SEQID_EN4B 10 #define SEQID_BRWR 11 +#define SEQID_RDAR 12 +#define SEQID_WRAR 13 + #define QUADSPI_MIN_IOMAP SZ_4M @@ -470,6 +473,28 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base)); + /* + * Read any device register. + * Used for Spansion S25FS-S family flash only. + */ + lut_base = SEQID_RDAR * 4; + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) | + LUT1(ADDR, PAD1, ADDR24BIT), + base + QUADSPI_LUT(lut_base)); + qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1), + base + QUADSPI_LUT(lut_base + 1)); + + /* + * Write any device register. + * Used for Spansion S25FS-S family flash only. + */ + lut_base = SEQID_WRAR * 4; + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) | + LUT1(ADDR, PAD1, ADDR24BIT), + base + QUADSPI_LUT(lut_base)); + qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1), + base + QUADSPI_LUT(lut_base + 1)); + fsl_qspi_lock_lut(q); } @@ -477,9 +502,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { + case SPINOR_OP_READ4_1_1_4: case SPINOR_OP_READ_1_1_4: case SPINOR_OP_READ_FAST: + case SPINOR_OP_READ4_FAST: return SEQID_READ; + case SPINOR_OP_SPANSION_RDAR: + return SEQID_RDAR; + case SPINOR_OP_SPANSION_WRAR: + return SEQID_WRAR; case SPINOR_OP_WREN: return SEQID_WREN; case SPINOR_OP_WRDI: @@ -491,6 +522,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) case SPINOR_OP_CHIP_ERASE: return SEQID_CHIP_ERASE; case SPINOR_OP_PP: + case SPINOR_OP_PP_4B: return SEQID_PP; case SPINOR_OP_RDID: return SEQID_RDID; @@ -830,8 +862,12 @@ static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) { int ret; struct fsl_qspi *q = nor->priv; + u32 to = 0; + + if (opcode == SPINOR_OP_SPANSION_RDAR) + memcpy(&to, nor->cmd_buf, 4); - ret = fsl_qspi_runcmd(q, opcode, 0, len); + ret = fsl_qspi_runcmd(q, opcode, to, len); if (ret) return ret; @@ -843,9 +879,13 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) { struct fsl_qspi *q = nor->priv; int ret; + u32 to = 0; + + if (opcode == SPINOR_OP_SPANSION_WRAR) + memcpy(&to, nor->cmd_buf, 4); if (!buf) { - ret = fsl_qspi_runcmd(q, opcode, 0, 1); + ret = fsl_qspi_runcmd(q, opcode, to, 1); if (ret) return ret; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index c425c7b..db3fe42 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -75,6 +75,10 @@ /* Used for Spansion flashes only. */ #define SPINOR_OP_BRWR 0x17 /* Bank register write */ +/* Used for Spansion S25FS-S family flash only. */ +#define SPINOR_OP_SPANSION_RDAR 0x65 /* Read any device register */ +#define SPINOR_OP_SPANSION_WRAR 0x71 /* Write any device register */ + /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ -- 2.1.0.27.g96db324 From mboxrd@z Thu Jan 1 00:00:00 1970 From: B56489@freescale.com (Yunhui Cui) Date: Thu, 18 Aug 2016 15:37:59 +0800 Subject: [PATCH v3 4/9] mtd: spi-nor: fsl-quadspi: extend support for some special requerment. In-Reply-To: <1471505884-33996-1-git-send-email-B56489@freescale.com> References: <1471505884-33996-1-git-send-email-B56489@freescale.com> Message-ID: <1471505884-33996-4-git-send-email-B56489@freescale.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Yunhui Cui Add extra info in LUT table to support some special requerments. Spansion S25FS-S family flash need some special operations. Signed-off-by: Yunhui Cui --- drivers/mtd/spi-nor/fsl-quadspi.c | 44 +++++++++++++++++++++++++++++++++++++-- include/linux/mtd/spi-nor.h | 4 ++++ 2 files changed, 46 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index b0a74b8..2521370 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -205,6 +205,9 @@ #define SEQID_RDCR 9 #define SEQID_EN4B 10 #define SEQID_BRWR 11 +#define SEQID_RDAR 12 +#define SEQID_WRAR 13 + #define QUADSPI_MIN_IOMAP SZ_4M @@ -470,6 +473,28 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base)); + /* + * Read any device register. + * Used for Spansion S25FS-S family flash only. + */ + lut_base = SEQID_RDAR * 4; + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) | + LUT1(ADDR, PAD1, ADDR24BIT), + base + QUADSPI_LUT(lut_base)); + qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1), + base + QUADSPI_LUT(lut_base + 1)); + + /* + * Write any device register. + * Used for Spansion S25FS-S family flash only. + */ + lut_base = SEQID_WRAR * 4; + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) | + LUT1(ADDR, PAD1, ADDR24BIT), + base + QUADSPI_LUT(lut_base)); + qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1), + base + QUADSPI_LUT(lut_base + 1)); + fsl_qspi_lock_lut(q); } @@ -477,9 +502,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { + case SPINOR_OP_READ4_1_1_4: case SPINOR_OP_READ_1_1_4: case SPINOR_OP_READ_FAST: + case SPINOR_OP_READ4_FAST: return SEQID_READ; + case SPINOR_OP_SPANSION_RDAR: + return SEQID_RDAR; + case SPINOR_OP_SPANSION_WRAR: + return SEQID_WRAR; case SPINOR_OP_WREN: return SEQID_WREN; case SPINOR_OP_WRDI: @@ -491,6 +522,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) case SPINOR_OP_CHIP_ERASE: return SEQID_CHIP_ERASE; case SPINOR_OP_PP: + case SPINOR_OP_PP_4B: return SEQID_PP; case SPINOR_OP_RDID: return SEQID_RDID; @@ -830,8 +862,12 @@ static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) { int ret; struct fsl_qspi *q = nor->priv; + u32 to = 0; + + if (opcode == SPINOR_OP_SPANSION_RDAR) + memcpy(&to, nor->cmd_buf, 4); - ret = fsl_qspi_runcmd(q, opcode, 0, len); + ret = fsl_qspi_runcmd(q, opcode, to, len); if (ret) return ret; @@ -843,9 +879,13 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) { struct fsl_qspi *q = nor->priv; int ret; + u32 to = 0; + + if (opcode == SPINOR_OP_SPANSION_WRAR) + memcpy(&to, nor->cmd_buf, 4); if (!buf) { - ret = fsl_qspi_runcmd(q, opcode, 0, 1); + ret = fsl_qspi_runcmd(q, opcode, to, 1); if (ret) return ret; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index c425c7b..db3fe42 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -75,6 +75,10 @@ /* Used for Spansion flashes only. */ #define SPINOR_OP_BRWR 0x17 /* Bank register write */ +/* Used for Spansion S25FS-S family flash only. */ +#define SPINOR_OP_SPANSION_RDAR 0x65 /* Read any device register */ +#define SPINOR_OP_SPANSION_WRAR 0x71 /* Write any device register */ + /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ -- 2.1.0.27.g96db324