From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753905AbcHRJ1Z (ORCPT ); Thu, 18 Aug 2016 05:27:25 -0400 Received: from mail-co1nam03on0132.outbound.protection.outlook.com ([104.47.40.132]:53523 "EHLO NAM03-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752864AbcHRJ1M (ORCPT ); Thu, 18 Aug 2016 05:27:12 -0400 Authentication-Results: spf=neutral (sender IP is 192.88.168.50) smtp.mailfrom=freescale.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=none action=none header.from=freescale.com;nxp.com; dkim=none (message not signed) header.d=none; From: Yunhui Cui To: , , , CC: , , , , Yunhui Cui Subject: [PATCH v3 8/9] mtd: fsl-quadspi: disable AHB buffer prefetch Date: Thu, 18 Aug 2016 15:38:03 +0800 Message-ID: <1471505884-33996-8-git-send-email-B56489@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 In-Reply-To: <1471505884-33996-1-git-send-email-B56489@freescale.com> References: <1471505884-33996-1-git-send-email-B56489@freescale.com> X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:192.88.168.50;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(7916002)(2980300002)(199003)(189002)(50944005)(19580395003)(8936002)(356003)(77096005)(50466002)(50986999)(229853001)(68736007)(81166006)(104016004)(2950100001)(575784001)(305945005)(76176999)(586003)(81156014)(2906002)(2201001)(36756003)(105606002)(19580405001)(7846002)(47776003)(5003940100001)(97736004)(50226002)(626004)(189998001)(5001770100001)(11100500001)(4326007)(92566002)(106466001)(8666005)(48376002)(8676002)(87936001)(7059030);DIR:OUT;SFP:1102;SCL:1;SRVR:DM5PR03MB2682;H:tx30smr01.am.freescale.net;FPR:;SPF:Neutral;PTR:InfoDomainNonexistent;A:1;MX:1;LANG:en; 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The buffer pre-fetch is enabled if the fetch size as configured either in the LUT or in the BUFxCR register is greater than 8 bytes. Impact: Only 64 bit read allowed. Workaround: Keep the read data size to 64 bits (8 Bytes), which disables the prefetch on the AHB buffer, and prevents this issue from occurring. Signed-off-by: Yunhui Cui --- drivers/mtd/spi-nor/fsl-quadspi.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index f9a7d4b..193e81b 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -41,6 +41,8 @@ #define QUADSPI_QUIRK_TKT253890 (1 << 2) /* Controller cannot wake up from wait mode, TKT245618 */ #define QUADSPI_QUIRK_TKT245618 (1 << 3) +/*Errata A-009282: disable the AHB buffer prefetch */ +#define QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT (1 << 4) /* QSPI_AMBA_BASE is internally added by SOC design */ #define QUADSPI_AMBA_BASE_INTERNAL (0x10000) @@ -270,7 +272,7 @@ static struct fsl_qspi_devtype_data ls1021a_data = { .rxfifo = 128, .txfifo = 64, .ahb_buf_size = 1024, - .driver_data = 0, + .driver_data = QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT, }; static struct fsl_qspi_devtype_data ls2080a_data = { @@ -278,7 +280,8 @@ static struct fsl_qspi_devtype_data ls2080a_data = { .rxfifo = 128, .txfifo = 64, .ahb_buf_size = 1024, - .driver_data = QUADSPI_AMBA_BASE_INTERNAL, + .driver_data = QUADSPI_AMBA_BASE_INTERNAL + | QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT, }; #define FSL_QSPI_MAX_CHIP 4 @@ -328,6 +331,11 @@ static inline int has_added_amba_base_internal(struct fsl_qspi *q) return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL; } +static inline int needs_disable_ahb_prefetch(struct fsl_qspi *q) +{ + return q->devtype_data->driver_data & QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT; +} + /* * R/W functions for big- or little-endian registers: * The qSPI controller's endian is independent of the CPU core's endian. @@ -757,14 +765,21 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); - /* - * Set ADATSZ with the maximum AHB buffer size to improve the - * read performance. - */ - qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | - ((q->devtype_data->ahb_buf_size / 8) - << QUADSPI_BUF3CR_ADATSZ_SHIFT), + + if (needs_disable_ahb_prefetch(q)) { + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | + (1 << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR); + } else { + /* + * Set ADATSZ with the maximum AHB buffer size to improve the + * read performance. + */ + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | + ((q->devtype_data->ahb_buf_size / 8) + << QUADSPI_BUF3CR_ADATSZ_SHIFT), + base + QUADSPI_BUF3CR); + } /* We only use the buffer3 */ qspi_writel(q, 0, base + QUADSPI_BUF0IND); -- 2.1.0.27.g96db324 From mboxrd@z Thu Jan 1 00:00:00 1970 From: B56489@freescale.com (Yunhui Cui) Date: Thu, 18 Aug 2016 15:38:03 +0800 Subject: [PATCH v3 8/9] mtd: fsl-quadspi: disable AHB buffer prefetch In-Reply-To: <1471505884-33996-1-git-send-email-B56489@freescale.com> References: <1471505884-33996-1-git-send-email-B56489@freescale.com> Message-ID: <1471505884-33996-8-git-send-email-B56489@freescale.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Yunhui Cui A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data Affects: QuadSPI Description: With AHB buffer prefetch enabled, the QuadSPI may return incorrect data on the AHB interface. The buffer pre-fetch is enabled if the fetch size as configured either in the LUT or in the BUFxCR register is greater than 8 bytes. Impact: Only 64 bit read allowed. Workaround: Keep the read data size to 64 bits (8 Bytes), which disables the prefetch on the AHB buffer, and prevents this issue from occurring. Signed-off-by: Yunhui Cui --- drivers/mtd/spi-nor/fsl-quadspi.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index f9a7d4b..193e81b 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -41,6 +41,8 @@ #define QUADSPI_QUIRK_TKT253890 (1 << 2) /* Controller cannot wake up from wait mode, TKT245618 */ #define QUADSPI_QUIRK_TKT245618 (1 << 3) +/*Errata A-009282: disable the AHB buffer prefetch */ +#define QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT (1 << 4) /* QSPI_AMBA_BASE is internally added by SOC design */ #define QUADSPI_AMBA_BASE_INTERNAL (0x10000) @@ -270,7 +272,7 @@ static struct fsl_qspi_devtype_data ls1021a_data = { .rxfifo = 128, .txfifo = 64, .ahb_buf_size = 1024, - .driver_data = 0, + .driver_data = QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT, }; static struct fsl_qspi_devtype_data ls2080a_data = { @@ -278,7 +280,8 @@ static struct fsl_qspi_devtype_data ls2080a_data = { .rxfifo = 128, .txfifo = 64, .ahb_buf_size = 1024, - .driver_data = QUADSPI_AMBA_BASE_INTERNAL, + .driver_data = QUADSPI_AMBA_BASE_INTERNAL + | QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT, }; #define FSL_QSPI_MAX_CHIP 4 @@ -328,6 +331,11 @@ static inline int has_added_amba_base_internal(struct fsl_qspi *q) return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL; } +static inline int needs_disable_ahb_prefetch(struct fsl_qspi *q) +{ + return q->devtype_data->driver_data & QUADSPI_QUIRK_ADASZ_8BYTE_LIMIT; +} + /* * R/W functions for big- or little-endian registers: * The qSPI controller's endian is independent of the CPU core's endian. @@ -757,14 +765,21 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); - /* - * Set ADATSZ with the maximum AHB buffer size to improve the - * read performance. - */ - qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | - ((q->devtype_data->ahb_buf_size / 8) - << QUADSPI_BUF3CR_ADATSZ_SHIFT), + + if (needs_disable_ahb_prefetch(q)) { + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | + (1 << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR); + } else { + /* + * Set ADATSZ with the maximum AHB buffer size to improve the + * read performance. + */ + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | + ((q->devtype_data->ahb_buf_size / 8) + << QUADSPI_BUF3CR_ADATSZ_SHIFT), + base + QUADSPI_BUF3CR); + } /* We only use the buffer3 */ qspi_writel(q, 0, base + QUADSPI_BUF0IND); -- 2.1.0.27.g96db324