From mboxrd@z Thu Jan 1 00:00:00 1970 From: Brijesh Singh Subject: [RFC PATCH v1 13/28] iommu/amd: AMD IOMMU support for SEV Date: Mon, 22 Aug 2016 19:26:13 -0400 Message-ID: <147190837333.9523.16962214308407411754.stgit__28082.6007751331$1471910301$gmane$org@brijesh-build-machine> References: <147190820782.9523.4967724730957229273.stgit@brijesh-build-machine> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Received: from mail-co1nam03on0046.outbound.protection.outlook.com ([104.47.40.46]:16725 "EHLO NAM03-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755825AbcHVX6C (ORCPT ); Mon, 22 Aug 2016 19:58:02 -0400 In-Reply-To: <147190820782.9523.4967724730957229273.stgit@brijesh-build-machine> Sender: linux-crypto-owner@vger.kernel.org List-ID: From: Tom Lendacky DMA must be performed to memory that is not mapped encrypted when running with SEV active. So if SEV is active, do not return the encryption mask to the IOMMU. Signed-off-by: Tom Lendacky --- arch/x86/mm/mem_encrypt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index ce6e3ea..d6e9f96 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -237,7 +237,7 @@ void __init mem_encrypt_init(void) unsigned long amd_iommu_get_me_mask(void) { - return sme_me_mask; + return sev_active ? 0 : sme_me_mask; } unsigned long swiotlb_get_me_mask(void)