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From: Fabio Estevam <festevam@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 2/3] mx6ul_14x14_evk: Adjust SPL DDR3 settings
Date: Mon, 29 Aug 2016 14:56:15 -0300	[thread overview]
Message-ID: <1472493376-7697-2-git-send-email-festevam@gmail.com> (raw)
In-Reply-To: <1472493376-7697-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam@nxp.com>

Adjust DDR3 initialization done in SPL by comparing them against
the NXP DCD table.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
Changes since v1:
- Fix more mismatches

 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index c213861..b13f0e2 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -777,17 +777,17 @@ static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 	.dram_odt0 = 0x00000030,
 	.dram_odt1 = 0x00000030,
 	.dram_sdba2 = 0x00000000,
-	.dram_sdclk_0 = 0x00000008,
-	.dram_sdqs0 = 0x00000038,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00000030,
 	.dram_sdqs1 = 0x00000030,
 	.dram_reset = 0x00000030,
 };
 
 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
-	.p0_mpwldectrl0 = 0x00070007,
-	.p0_mpdgctrl0 = 0x41490145,
-	.p0_mprddlctl = 0x40404546,
-	.p0_mpwrdlctl = 0x4040524D,
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x41570155,
+	.p0_mprddlctl = 0x4040474A,
+	.p0_mpwrdlctl = 0x40405550,
 };
 
 struct mx6_ddr_sysinfo ddr_sysinfo = {
@@ -797,7 +797,7 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.cs1_mirror = 0,
 	.rtt_wr = 2,
 	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
-	.walat = 1,		/* Write additional latency */
+	.walat = 0,		/* Write additional latency */
 	.ralat = 5,		/* Read additional latency */
 	.mif3_mode = 3,		/* Command prediction working mode */
 	.bi_on = 1,		/* Bank interleaving enabled */
-- 
1.9.1

  reply	other threads:[~2016-08-29 17:56 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-29 17:56 [U-Boot] [PATCH v2 1/3] mx6: ddr: Adjust MDREF register settings for MX6UL Fabio Estevam
2016-08-29 17:56 ` Fabio Estevam [this message]
2016-08-29 17:56 ` [U-Boot] [PATCH v2 3/3] mx6ul_14x14_ev: Enable the CCGR clocks earlier Fabio Estevam
2016-08-29 18:22   ` Eric Nelson
2016-08-29 18:48 ` [U-Boot] [PATCH v2 1/3] mx6: ddr: Adjust MDREF register settings for MX6UL Eric Nelson
2016-08-29 19:17   ` Eric Nelson
2016-08-29 19:53   ` Fabio Estevam
2016-08-29 20:40     ` Eric Nelson
  -- strict thread matches above, loose matches on Subject: below --
2016-08-29 17:54 Fabio Estevam
2016-08-29 17:54 ` [U-Boot] [PATCH v2 2/3] mx6ul_14x14_evk: Adjust SPL DDR3 settings Fabio Estevam

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