From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932170AbcIBL0e (ORCPT ); Fri, 2 Sep 2016 07:26:34 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:19135 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753155AbcIBL0Y (ORCPT ); Fri, 2 Sep 2016 07:26:24 -0400 From: YT Shen To: , Philipp Zabel CC: David Airlie , Matthias Brugger , YT Shen , Daniel Kurtz , Mao Huang , CK Hu , Bibby Hsieh , Daniel Vetter , Thierry Reding , Jie Qiu , Maxime Ripard , Chris Wilson , shaoming chen , Jitao Shi , Boris Brezillon , Dan Carpenter , , , , , Sascha Hauer , , Subject: [PATCH v7 9/9] drm/mediatek: add support for Mediatek SoC MT2701 Date: Fri, 2 Sep 2016 19:24:44 +0800 Message-ID: <1472815484-43821-10-git-send-email-yt.shen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add support for the Mediatek MT2701 DISP subsystem. There is only one OVL engine in MT2701. Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 17 +++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 7 +++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 29 +++++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 6 ++++++ 8 files changed, 73 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index eb5c05e..1da0a71 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -286,11 +286,17 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) return 0; } +static const struct mtk_ddp_comp_driver_data mt2701_ovl_driver_data = { + .ovl = {0x0040, 1 << 12, 0} +}; + static const struct mtk_ddp_comp_driver_data mt8173_ovl_driver_data = { .ovl = {0x0f40, 0, 1 << 12} }; static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-ovl", + .data = &mt2701_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index fb0db50..506a353 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -225,11 +225,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) return 0; } +static const struct mtk_ddp_comp_driver_data mt2701_rdma_driver_data = { + .rdma_fifo_pseudo_size = SZ_4K, +}; + static const struct mtk_ddp_comp_driver_data mt8173_rdma_driver_data = { .rdma_fifo_pseudo_size = SZ_8K, }; static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-rdma", + .data = &mt2701_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index a9b209c..8130f3d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -60,6 +60,13 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) #define MT8173_MUTEX_MOD_DISP_OD BIT(25) +#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) +#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) +#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) +#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) +#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) +#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) + #define MUTEX_SOF_SINGLE_MODE 0 #define MUTEX_SOF_DSI0 1 #define MUTEX_SOF_DSI1 2 @@ -92,6 +99,15 @@ struct mtk_ddp { const unsigned int *mutex_mod; }; +static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, + [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, + [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, + [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, +}; + static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, @@ -390,6 +406,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) } static const struct of_device_id ddp_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, {}, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 4b4e449..465819b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -112,6 +112,7 @@ struct mtk_ddp_comp_match { static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, NULL }, + [DDP_COMPONENT_BLS] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, @@ -130,11 +131,17 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, }; +static const struct mtk_ddp_comp_driver_data mt2701_color_driver_data = { + .color_offset = 0x0f00, +}; + static const struct mtk_ddp_comp_driver_data mt8173_color_driver_data = { .color_offset = 0x0c00, }; static const struct of_device_id mtk_disp_color_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-color", + .data = &mt2701_color_driver_data}, { .compatible = "mediatek,mt8173-disp-color", .data = &mt8173_color_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 53065c7..0850aa4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -40,6 +40,7 @@ enum mtk_ddp_comp_type { enum mtk_ddp_comp_id { DDP_COMPONENT_AAL, + DDP_COMPONENT_BLS, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DPI0, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6dbe963..167f716 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -109,6 +109,19 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { .atomic_commit = mtk_atomic_commit, }; +static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_BLS, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, @@ -128,6 +141,14 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { + .main_path = mt2701_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), + .ext_path = mt2701_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), + .shadow_register = true, +}; + static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .main_path = mt8173_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), @@ -323,16 +344,22 @@ static const struct component_master_ops mtk_drm_ops = { }; static const struct of_device_id mtk_ddp_comp_dt_ids[] = { + { .compatible = "mediatek,mt2701-disp-ovl", .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, + { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, + { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, { } @@ -505,6 +532,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, mtk_drm_sys_resume); static const struct of_device_id mtk_drm_of_ids[] = { + { .compatible = "mediatek,mt2701-mmsys", + .data = &mt2701_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, { } diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index f807621..98a9775 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -1215,6 +1215,7 @@ static int mtk_dsi_remove(struct platform_device *pdev) } static const struct of_device_id mtk_dsi_of_match[] = { + { .compatible = "mediatek,mt2701-dsi" }, { .compatible = "mediatek,mt8173-dsi" }, { }, }; diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index 34e95c6..944fb1d 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -467,11 +467,17 @@ static int mtk_mipi_tx_remove(struct platform_device *pdev) return 0; } +static const struct mtk_mipitx_data mt2701_mipitx_data = { + .data = (3 << 8) +}; + static const struct mtk_mipitx_data mt8173_mipitx_data = { .data = (0 << 8) }; static const struct of_device_id mtk_mipi_tx_match[] = { + { .compatible = "mediatek,mt2701-mipi-tx", + .data = &mt2701_mipitx_data }, { .compatible = "mediatek,mt8173-mipi-tx", .data = &mt8173_mipitx_data }, {}, -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: YT Shen Subject: [PATCH v7 9/9] drm/mediatek: add support for Mediatek SoC MT2701 Date: Fri, 2 Sep 2016 19:24:44 +0800 Message-ID: <1472815484-43821-10-git-send-email-yt.shen@mediatek.com> References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org, Philipp Zabel Cc: Daniel Vetter , Jie Qiu , Mao Huang , yingjoe.chen@mediatek.com, Dan Carpenter , Jitao Shi , linux-mediatek@lists.infradead.org, Matthias Brugger , shaoming chen , linux-arm-kernel@lists.infradead.org, srv_heupstream@mediatek.com, emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Sascha Hauer , Maxime Ripard List-Id: linux-mediatek@lists.infradead.org VGhpcyBwYXRjaCBhZGQgc3VwcG9ydCBmb3IgdGhlIE1lZGlhdGVrIE1UMjcwMSBESVNQIHN1YnN5 c3RlbS4KVGhlcmUgaXMgb25seSBvbmUgT1ZMIGVuZ2luZSBpbiBNVDI3MDEuCgpTaWduZWQtb2Zm LWJ5OiBZVCBTaGVuIDx5dC5zaGVuQG1lZGlhdGVrLmNvbT4KLS0tCiBkcml2ZXJzL2dwdS9kcm0v bWVkaWF0ZWsvbXRrX2Rpc3Bfb3ZsLmMgICAgIHwgIDYgKysrKysrCiBkcml2ZXJzL2dwdS9kcm0v bWVkaWF0ZWsvbXRrX2Rpc3BfcmRtYS5jICAgIHwgIDYgKysrKysrCiBkcml2ZXJzL2dwdS9kcm0v bWVkaWF0ZWsvbXRrX2RybV9kZHAuYyAgICAgIHwgMTcgKysrKysrKysrKysrKysrKysKIGRyaXZl cnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmMgfCAgNyArKysrKysrCiBkcml2 ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5oIHwgIDEgKwogZHJpdmVycy9n cHUvZHJtL21lZGlhdGVrL210a19kcm1fZHJ2LmMgICAgICB8IDI5ICsrKysrKysrKysrKysrKysr KysrKysrKysrKysrCiBkcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RzaS5jICAgICAgICAg IHwgIDEgKwogZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19taXBpX3R4LmMgICAgICB8ICA2 ICsrKysrKwogOCBmaWxlcyBjaGFuZ2VkLCA3MyBpbnNlcnRpb25zKCspCgpkaWZmIC0tZ2l0IGEv ZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kaXNwX292bC5jIGIvZHJpdmVycy9ncHUvZHJt L21lZGlhdGVrL210a19kaXNwX292bC5jCmluZGV4IGViNWMwNWUuLjFkYTBhNzEgMTAwNjQ0Ci0t LSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZGlzcF9vdmwuYworKysgYi9kcml2ZXJz L2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2Rpc3Bfb3ZsLmMKQEAgLTI4NiwxMSArMjg2LDE3IEBAIHN0 YXRpYyBpbnQgbXRrX2Rpc3Bfb3ZsX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2 KQogCXJldHVybiAwOwogfQogCitzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9kcml2 ZXJfZGF0YSBtdDI3MDFfb3ZsX2RyaXZlcl9kYXRhID0geworCS5vdmwgPSB7MHgwMDQwLCAxIDw8 IDEyLCAwfQorfTsKKwogc3RhdGljIGNvbnN0IHN0cnVjdCBtdGtfZGRwX2NvbXBfZHJpdmVyX2Rh dGEgbXQ4MTczX292bF9kcml2ZXJfZGF0YSA9IHsKIAkub3ZsID0gezB4MGY0MCwgMCwgMSA8PCAx Mn0KIH07CiAKIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIG10a19kaXNwX292bF9k cml2ZXJfZHRfbWF0Y2hbXSA9IHsKKwl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10MjcwMS1k aXNwLW92bCIsCisJICAuZGF0YSA9ICZtdDI3MDFfb3ZsX2RyaXZlcl9kYXRhfSwKIAl7IC5jb21w YXRpYmxlID0gIm1lZGlhdGVrLG10ODE3My1kaXNwLW92bCIsCiAJICAuZGF0YSA9ICZtdDgxNzNf b3ZsX2RyaXZlcl9kYXRhfSwKIAl7fSwKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9tdGtfZGlzcF9yZG1hLmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2Rpc3Bf cmRtYS5jCmluZGV4IGZiMGRiNTAuLjUwNmEzNTMgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2Ry bS9tZWRpYXRlay9tdGtfZGlzcF9yZG1hLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVr L210a19kaXNwX3JkbWEuYwpAQCAtMjI1LDExICsyMjUsMTcgQEAgc3RhdGljIGludCBtdGtfZGlz cF9yZG1hX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQogCXJldHVybiAwOwog fQogCitzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9kcml2ZXJfZGF0YSBtdDI3MDFf cmRtYV9kcml2ZXJfZGF0YSA9IHsKKwkucmRtYV9maWZvX3BzZXVkb19zaXplID0gU1pfNEssCit9 OworCiBzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9kcml2ZXJfZGF0YSBtdDgxNzNf cmRtYV9kcml2ZXJfZGF0YSA9IHsKIAkucmRtYV9maWZvX3BzZXVkb19zaXplID0gU1pfOEssCiB9 OwogCiBzdGF0aWMgY29uc3Qgc3RydWN0IG9mX2RldmljZV9pZCBtdGtfZGlzcF9yZG1hX2RyaXZl cl9kdF9tYXRjaFtdID0geworCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQyNzAxLWRpc3At cmRtYSIsCisJICAuZGF0YSA9ICZtdDI3MDFfcmRtYV9kcml2ZXJfZGF0YX0sCiAJeyAuY29tcGF0 aWJsZSA9ICJtZWRpYXRlayxtdDgxNzMtZGlzcC1yZG1hIiwKIAkgIC5kYXRhID0gJm10ODE3M19y ZG1hX2RyaXZlcl9kYXRhfSwKIAl7fSwKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9tdGtfZHJtX2RkcC5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRw LmMKaW5kZXggYTliMjA5Yy4uODEzMGYzZCAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL21l ZGlhdGVrL210a19kcm1fZGRwLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19k cm1fZGRwLmMKQEAgLTYwLDYgKzYwLDEzIEBACiAjZGVmaW5lIE1UODE3M19NVVRFWF9NT0RfRElT UF9QV00xCQlCSVQoMjQpCiAjZGVmaW5lIE1UODE3M19NVVRFWF9NT0RfRElTUF9PRAkJQklUKDI1 KQogCisjZGVmaW5lIE1UMjcwMV9NVVRFWF9NT0RfRElTUF9PVkwJCUJJVCgzKQorI2RlZmluZSBN VDI3MDFfTVVURVhfTU9EX0RJU1BfV0RNQQkJQklUKDYpCisjZGVmaW5lIE1UMjcwMV9NVVRFWF9N T0RfRElTUF9DT0xPUgkJQklUKDcpCisjZGVmaW5lIE1UMjcwMV9NVVRFWF9NT0RfRElTUF9CTFMJ CUJJVCg5KQorI2RlZmluZSBNVDI3MDFfTVVURVhfTU9EX0RJU1BfUkRNQTAJCUJJVCgxMCkKKyNk ZWZpbmUgTVQyNzAxX01VVEVYX01PRF9ESVNQX1JETUExCQlCSVQoMTIpCisKICNkZWZpbmUgTVVU RVhfU09GX1NJTkdMRV9NT0RFCQkwCiAjZGVmaW5lIE1VVEVYX1NPRl9EU0kwCQkJMQogI2RlZmlu ZSBNVVRFWF9TT0ZfRFNJMQkJCTIKQEAgLTkyLDYgKzk5LDE1IEBAIHN0cnVjdCBtdGtfZGRwIHsK IAljb25zdCB1bnNpZ25lZCBpbnQJCSptdXRleF9tb2Q7CiB9OwogCitzdGF0aWMgY29uc3QgdW5z aWduZWQgaW50IG10MjcwMV9tdXRleF9tb2RbRERQX0NPTVBPTkVOVF9JRF9NQVhdID0geworCVtE RFBfQ09NUE9ORU5UX0JMU10gPSBNVDI3MDFfTVVURVhfTU9EX0RJU1BfQkxTLAorCVtERFBfQ09N UE9ORU5UX0NPTE9SMF0gPSBNVDI3MDFfTVVURVhfTU9EX0RJU1BfQ09MT1IsCisJW0REUF9DT01Q T05FTlRfT1ZMMF0gPSBNVDI3MDFfTVVURVhfTU9EX0RJU1BfT1ZMLAorCVtERFBfQ09NUE9ORU5U X1JETUEwXSA9IE1UMjcwMV9NVVRFWF9NT0RfRElTUF9SRE1BMCwKKwlbRERQX0NPTVBPTkVOVF9S RE1BMV0gPSBNVDI3MDFfTVVURVhfTU9EX0RJU1BfUkRNQTEsCisJW0REUF9DT01QT05FTlRfV0RN QTBdID0gTVQyNzAxX01VVEVYX01PRF9ESVNQX1dETUEsCit9OworCiBzdGF0aWMgY29uc3QgdW5z aWduZWQgaW50IG10ODE3M19tdXRleF9tb2RbRERQX0NPTVBPTkVOVF9JRF9NQVhdID0gewogCVtE RFBfQ09NUE9ORU5UX0FBTF0gPSBNVDgxNzNfTVVURVhfTU9EX0RJU1BfQUFMLAogCVtERFBfQ09N UE9ORU5UX0NPTE9SMF0gPSBNVDgxNzNfTVVURVhfTU9EX0RJU1BfQ09MT1IwLApAQCAtMzkwLDYg KzQwNiw3IEBAIHN0YXRpYyBpbnQgbXRrX2RkcF9yZW1vdmUoc3RydWN0IHBsYXRmb3JtX2Rldmlj ZSAqcGRldikKIH0KIAogc3RhdGljIGNvbnN0IHN0cnVjdCBvZl9kZXZpY2VfaWQgZGRwX2RyaXZl cl9kdF9tYXRjaFtdID0geworCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQyNzAxLWRpc3At bXV0ZXgiLCAuZGF0YSA9IG10MjcwMV9tdXRleF9tb2R9LAogCXsgLmNvbXBhdGlibGUgPSAibWVk aWF0ZWssbXQ4MTczLWRpc3AtbXV0ZXgiLCAuZGF0YSA9IG10ODE3M19tdXRleF9tb2R9LAogCXt9 LAogfTsKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9j b21wLmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jCmluZGV4 IDRiNGU0NDkuLjQ2NTgxOWIgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9t dGtfZHJtX2RkcF9jb21wLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1f ZGRwX2NvbXAuYwpAQCAtMTEyLDYgKzExMiw3IEBAIHN0cnVjdCBtdGtfZGRwX2NvbXBfbWF0Y2gg ewogCiBzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9tYXRjaCBtdGtfZGRwX21hdGNo ZXNbRERQX0NPTVBPTkVOVF9JRF9NQVhdID0gewogCVtERFBfQ09NUE9ORU5UX0FBTF0JPSB7IE1U S19ESVNQX0FBTCwJMCwgTlVMTCB9LAorCVtERFBfQ09NUE9ORU5UX0JMU10JPSB7IE1US19ESVNQ X1BXTSwJMCwgTlVMTCB9LAogCVtERFBfQ09NUE9ORU5UX0NPTE9SMF0JPSB7IE1US19ESVNQX0NP TE9SLAkwLCAmZGRwX2NvbG9yIH0sCiAJW0REUF9DT01QT05FTlRfQ09MT1IxXQk9IHsgTVRLX0RJ U1BfQ09MT1IsCTEsICZkZHBfY29sb3IgfSwKIAlbRERQX0NPTVBPTkVOVF9EUEkwXQk9IHsgTVRL X0RQSSwJCTAsIE5VTEwgfSwKQEAgLTEzMCwxMSArMTMxLDE3IEBAIHN0YXRpYyBjb25zdCBzdHJ1 Y3QgbXRrX2RkcF9jb21wX21hdGNoIG10a19kZHBfbWF0Y2hlc1tERFBfQ09NUE9ORU5UX0lEX01B WF0gPSB7CiAJW0REUF9DT01QT05FTlRfV0RNQTFdCT0geyBNVEtfRElTUF9XRE1BLAkxLCBOVUxM IH0sCiB9OwogCitzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9kcml2ZXJfZGF0YSBt dDI3MDFfY29sb3JfZHJpdmVyX2RhdGEgPSB7CisJLmNvbG9yX29mZnNldCA9IDB4MGYwMCwKK307 CisKIHN0YXRpYyBjb25zdCBzdHJ1Y3QgbXRrX2RkcF9jb21wX2RyaXZlcl9kYXRhIG10ODE3M19j b2xvcl9kcml2ZXJfZGF0YSA9IHsKIAkuY29sb3Jfb2Zmc2V0ID0gMHgwYzAwLAogfTsKIAogc3Rh dGljIGNvbnN0IHN0cnVjdCBvZl9kZXZpY2VfaWQgbXRrX2Rpc3BfY29sb3JfZHJpdmVyX2R0X21h dGNoW10gPSB7CisJeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDI3MDEtZGlzcC1jb2xvciIs CisJICAuZGF0YSA9ICZtdDI3MDFfY29sb3JfZHJpdmVyX2RhdGF9LAogCXsgLmNvbXBhdGlibGUg PSAibWVkaWF0ZWssbXQ4MTczLWRpc3AtY29sb3IiLAogCSAgLmRhdGEgPSAmbXQ4MTczX2NvbG9y X2RyaXZlcl9kYXRhfSwKIAl7fSwKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRl ay9tdGtfZHJtX2RkcF9jb21wLmggYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9k ZHBfY29tcC5oCmluZGV4IDUzMDY1YzcuLjA4NTBhYTQgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1 L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmgKKysrIGIvZHJpdmVycy9ncHUvZHJtL21l ZGlhdGVrL210a19kcm1fZGRwX2NvbXAuaApAQCAtNDAsNiArNDAsNyBAQCBlbnVtIG10a19kZHBf Y29tcF90eXBlIHsKIAogZW51bSBtdGtfZGRwX2NvbXBfaWQgewogCUREUF9DT01QT05FTlRfQUFM LAorCUREUF9DT01QT05FTlRfQkxTLAogCUREUF9DT01QT05FTlRfQ09MT1IwLAogCUREUF9DT01Q T05FTlRfQ09MT1IxLAogCUREUF9DT01QT05FTlRfRFBJMCwKZGlmZiAtLWdpdCBhL2RyaXZlcnMv Z3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2Rydi5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVr L210a19kcm1fZHJ2LmMKaW5kZXggNmRiZTk2My4uMTY3ZjcxNiAxMDA2NDQKLS0tIGEvZHJpdmVy cy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZHJ2LmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21l ZGlhdGVrL210a19kcm1fZHJ2LmMKQEAgLTEwOSw2ICsxMDksMTkgQEAgc3RhdGljIGNvbnN0IHN0 cnVjdCBkcm1fbW9kZV9jb25maWdfZnVuY3MgbXRrX2RybV9tb2RlX2NvbmZpZ19mdW5jcyA9IHsK IAkuYXRvbWljX2NvbW1pdCA9IG10a19hdG9taWNfY29tbWl0LAogfTsKIAorc3RhdGljIGNvbnN0 IGVudW0gbXRrX2RkcF9jb21wX2lkIG10MjcwMV9tdGtfZGRwX21haW5bXSA9IHsKKwlERFBfQ09N UE9ORU5UX09WTDAsCisJRERQX0NPTVBPTkVOVF9SRE1BMCwKKwlERFBfQ09NUE9ORU5UX0NPTE9S MCwKKwlERFBfQ09NUE9ORU5UX0JMUywKKwlERFBfQ09NUE9ORU5UX0RTSTAsCit9OworCitzdGF0 aWMgY29uc3QgZW51bSBtdGtfZGRwX2NvbXBfaWQgbXQyNzAxX210a19kZHBfZXh0W10gPSB7CisJ RERQX0NPTVBPTkVOVF9SRE1BMSwKKwlERFBfQ09NUE9ORU5UX0RQSTAsCit9OworCiBzdGF0aWMg Y29uc3QgZW51bSBtdGtfZGRwX2NvbXBfaWQgbXQ4MTczX210a19kZHBfbWFpbltdID0gewogCURE UF9DT01QT05FTlRfT1ZMMCwKIAlERFBfQ09NUE9ORU5UX0NPTE9SMCwKQEAgLTEyOCw2ICsxNDEs MTQgQEAgc3RhdGljIGNvbnN0IGVudW0gbXRrX2RkcF9jb21wX2lkIG10ODE3M19tdGtfZGRwX2V4 dFtdID0gewogCUREUF9DT01QT05FTlRfRFBJMCwKIH07CiAKK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg bXRrX21tc3lzX2RyaXZlcl9kYXRhIG10MjcwMV9tbXN5c19kcml2ZXJfZGF0YSA9IHsKKwkubWFp bl9wYXRoID0gbXQyNzAxX210a19kZHBfbWFpbiwKKwkubWFpbl9sZW4gPSBBUlJBWV9TSVpFKG10 MjcwMV9tdGtfZGRwX21haW4pLAorCS5leHRfcGF0aCA9IG10MjcwMV9tdGtfZGRwX2V4dCwKKwku ZXh0X2xlbiA9IEFSUkFZX1NJWkUobXQyNzAxX210a19kZHBfZXh0KSwKKwkuc2hhZG93X3JlZ2lz dGVyID0gdHJ1ZSwKK307CisKIHN0YXRpYyBjb25zdCBzdHJ1Y3QgbXRrX21tc3lzX2RyaXZlcl9k YXRhIG10ODE3M19tbXN5c19kcml2ZXJfZGF0YSA9IHsKIAkubWFpbl9wYXRoID0gbXQ4MTczX210 a19kZHBfbWFpbiwKIAkubWFpbl9sZW4gPSBBUlJBWV9TSVpFKG10ODE3M19tdGtfZGRwX21haW4p LApAQCAtMzIzLDE2ICszNDQsMjIgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBjb21wb25lbnRfbWFz dGVyX29wcyBtdGtfZHJtX29wcyA9IHsKIH07CiAKIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2 aWNlX2lkIG10a19kZHBfY29tcF9kdF9pZHNbXSA9IHsKKwl7IC5jb21wYXRpYmxlID0gIm1lZGlh dGVrLG10MjcwMS1kaXNwLW92bCIsICAgLmRhdGEgPSAodm9pZCAqKU1US19ESVNQX09WTCB9LAog CXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLWRpc3Atb3ZsIiwgICAuZGF0YSA9ICh2 b2lkICopTVRLX0RJU1BfT1ZMIH0sCisJeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDI3MDEt ZGlzcC1yZG1hIiwgIC5kYXRhID0gKHZvaWQgKilNVEtfRElTUF9SRE1BIH0sCiAJeyAuY29tcGF0 aWJsZSA9ICJtZWRpYXRlayxtdDgxNzMtZGlzcC1yZG1hIiwgIC5kYXRhID0gKHZvaWQgKilNVEtf RElTUF9SRE1BIH0sCiAJeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDgxNzMtZGlzcC13ZG1h IiwgIC5kYXRhID0gKHZvaWQgKilNVEtfRElTUF9XRE1BIH0sCisJeyAuY29tcGF0aWJsZSA9ICJt ZWRpYXRlayxtdDI3MDEtZGlzcC1jb2xvciIsIC5kYXRhID0gKHZvaWQgKilNVEtfRElTUF9DT0xP UiB9LAogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLWRpc3AtY29sb3IiLCAuZGF0 YSA9ICh2b2lkICopTVRLX0RJU1BfQ09MT1IgfSwKIAl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVr LG10ODE3My1kaXNwLWFhbCIsICAgLmRhdGEgPSAodm9pZCAqKU1US19ESVNQX0FBTH0sCiAJeyAu Y29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDgxNzMtZGlzcC1nYW1tYSIsIC5kYXRhID0gKHZvaWQg KilNVEtfRElTUF9HQU1NQSwgfSwKIAl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10ODE3My1k aXNwLXVmb2UiLCAgLmRhdGEgPSAodm9pZCAqKU1US19ESVNQX1VGT0UgfSwKKwl7IC5jb21wYXRp YmxlID0gIm1lZGlhdGVrLG10MjcwMS1kc2kiLAkgICAgICAuZGF0YSA9ICh2b2lkICopTVRLX0RT SSB9LAogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLWRzaSIsICAgICAgICAuZGF0 YSA9ICh2b2lkICopTVRLX0RTSSB9LAogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTcz LWRwaSIsICAgICAgICAuZGF0YSA9ICh2b2lkICopTVRLX0RQSSB9LAorCXsgLmNvbXBhdGlibGUg PSAibWVkaWF0ZWssbXQyNzAxLWRpc3AtbXV0ZXgiLCAuZGF0YSA9ICh2b2lkICopTVRLX0RJU1Bf TVVURVggfSwKIAl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10ODE3My1kaXNwLW11dGV4Iiwg LmRhdGEgPSAodm9pZCAqKU1US19ESVNQX01VVEVYIH0sCisJeyAuY29tcGF0aWJsZSA9ICJtZWRp YXRlayxtdDI3MDEtZGlzcC1wd20iLCAgIC5kYXRhID0gKHZvaWQgKilNVEtfRElTUF9QV00gfSwK IAl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10ODE3My1kaXNwLXB3bSIsICAgLmRhdGEgPSAo dm9pZCAqKU1US19ESVNQX1BXTSB9LAogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTcz LWRpc3Atb2QiLCAgICAuZGF0YSA9ICh2b2lkICopTVRLX0RJU1BfT0QgfSwKIAl7IH0KQEAgLTUw NSw2ICs1MzIsOCBAQCBzdGF0aWMgU0lNUExFX0RFVl9QTV9PUFMobXRrX2RybV9wbV9vcHMsIG10 a19kcm1fc3lzX3N1c3BlbmQsCiAJCQkgbXRrX2RybV9zeXNfcmVzdW1lKTsKIAogc3RhdGljIGNv bnN0IHN0cnVjdCBvZl9kZXZpY2VfaWQgbXRrX2RybV9vZl9pZHNbXSA9IHsKKwl7IC5jb21wYXRp YmxlID0gIm1lZGlhdGVrLG10MjcwMS1tbXN5cyIsCisJICAuZGF0YSA9ICZtdDI3MDFfbW1zeXNf ZHJpdmVyX2RhdGF9LAogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLW1tc3lzIiwK IAkgIC5kYXRhID0gJm10ODE3M19tbXN5c19kcml2ZXJfZGF0YX0sCiAJeyB9CmRpZmYgLS1naXQg YS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RzaS5jIGIvZHJpdmVycy9ncHUvZHJtL21l ZGlhdGVrL210a19kc2kuYwppbmRleCBmODA3NjIxLi45OGE5Nzc1IDEwMDY0NAotLS0gYS9kcml2 ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RzaS5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9tdGtfZHNpLmMKQEAgLTEyMTUsNiArMTIxNSw3IEBAIHN0YXRpYyBpbnQgbXRrX2RzaV9y ZW1vdmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKIH0KIAogc3RhdGljIGNvbnN0IHN0 cnVjdCBvZl9kZXZpY2VfaWQgbXRrX2RzaV9vZl9tYXRjaFtdID0geworCXsgLmNvbXBhdGlibGUg PSAibWVkaWF0ZWssbXQyNzAxLWRzaSIgfSwKIAl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10 ODE3My1kc2kiIH0sCiAJeyB9LAogfTsKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9tdGtfbWlwaV90eC5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19taXBpX3R4 LmMKaW5kZXggMzRlOTVjNi4uOTQ0ZmIxZCAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL21l ZGlhdGVrL210a19taXBpX3R4LmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19t aXBpX3R4LmMKQEAgLTQ2NywxMSArNDY3LDE3IEBAIHN0YXRpYyBpbnQgbXRrX21pcGlfdHhfcmVt b3ZlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCiAJcmV0dXJuIDA7CiB9CiAKK3N0YXRp YyBjb25zdCBzdHJ1Y3QgbXRrX21pcGl0eF9kYXRhIG10MjcwMV9taXBpdHhfZGF0YSA9IHsKKwku ZGF0YSA9ICgzIDw8IDgpCit9OworCiBzdGF0aWMgY29uc3Qgc3RydWN0IG10a19taXBpdHhfZGF0 YSBtdDgxNzNfbWlwaXR4X2RhdGEgPSB7CiAJLmRhdGEgPSAoMCA8PCA4KQogfTsKIAogc3RhdGlj IGNvbnN0IHN0cnVjdCBvZl9kZXZpY2VfaWQgbXRrX21pcGlfdHhfbWF0Y2hbXSA9IHsKKwl7IC5j b21wYXRpYmxlID0gIm1lZGlhdGVrLG10MjcwMS1taXBpLXR4IiwKKwkgIC5kYXRhID0gJm10Mjcw MV9taXBpdHhfZGF0YSB9LAogCXsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLW1pcGkt dHgiLAogCSAgLmRhdGEgPSAmbXQ4MTczX21pcGl0eF9kYXRhIH0sCiAJe30sCi0tIAoxLjkuMQoK X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: yt.shen@mediatek.com (YT Shen) Date: Fri, 2 Sep 2016 19:24:44 +0800 Subject: [PATCH v7 9/9] drm/mediatek: add support for Mediatek SoC MT2701 In-Reply-To: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> Message-ID: <1472815484-43821-10-git-send-email-yt.shen@mediatek.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch add support for the Mediatek MT2701 DISP subsystem. There is only one OVL engine in MT2701. Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 17 +++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 7 +++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 29 +++++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 6 ++++++ 8 files changed, 73 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index eb5c05e..1da0a71 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -286,11 +286,17 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) return 0; } +static const struct mtk_ddp_comp_driver_data mt2701_ovl_driver_data = { + .ovl = {0x0040, 1 << 12, 0} +}; + static const struct mtk_ddp_comp_driver_data mt8173_ovl_driver_data = { .ovl = {0x0f40, 0, 1 << 12} }; static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-ovl", + .data = &mt2701_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index fb0db50..506a353 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -225,11 +225,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) return 0; } +static const struct mtk_ddp_comp_driver_data mt2701_rdma_driver_data = { + .rdma_fifo_pseudo_size = SZ_4K, +}; + static const struct mtk_ddp_comp_driver_data mt8173_rdma_driver_data = { .rdma_fifo_pseudo_size = SZ_8K, }; static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-rdma", + .data = &mt2701_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index a9b209c..8130f3d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -60,6 +60,13 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) #define MT8173_MUTEX_MOD_DISP_OD BIT(25) +#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) +#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) +#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) +#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) +#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) +#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) + #define MUTEX_SOF_SINGLE_MODE 0 #define MUTEX_SOF_DSI0 1 #define MUTEX_SOF_DSI1 2 @@ -92,6 +99,15 @@ struct mtk_ddp { const unsigned int *mutex_mod; }; +static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, + [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, + [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, + [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, +}; + static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, @@ -390,6 +406,7 @@ static int mtk_ddp_remove(struct platform_device *pdev) } static const struct of_device_id ddp_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, {}, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 4b4e449..465819b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -112,6 +112,7 @@ struct mtk_ddp_comp_match { static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, NULL }, + [DDP_COMPONENT_BLS] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, @@ -130,11 +131,17 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, }; +static const struct mtk_ddp_comp_driver_data mt2701_color_driver_data = { + .color_offset = 0x0f00, +}; + static const struct mtk_ddp_comp_driver_data mt8173_color_driver_data = { .color_offset = 0x0c00, }; static const struct of_device_id mtk_disp_color_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-color", + .data = &mt2701_color_driver_data}, { .compatible = "mediatek,mt8173-disp-color", .data = &mt8173_color_driver_data}, {}, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 53065c7..0850aa4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -40,6 +40,7 @@ enum mtk_ddp_comp_type { enum mtk_ddp_comp_id { DDP_COMPONENT_AAL, + DDP_COMPONENT_BLS, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DPI0, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6dbe963..167f716 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -109,6 +109,19 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { .atomic_commit = mtk_atomic_commit, }; +static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_BLS, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, @@ -128,6 +141,14 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { + .main_path = mt2701_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), + .ext_path = mt2701_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), + .shadow_register = true, +}; + static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .main_path = mt8173_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), @@ -323,16 +344,22 @@ static const struct component_master_ops mtk_drm_ops = { }; static const struct of_device_id mtk_ddp_comp_dt_ids[] = { + { .compatible = "mediatek,mt2701-disp-ovl", .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, + { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, + { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, { } @@ -505,6 +532,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, mtk_drm_sys_resume); static const struct of_device_id mtk_drm_of_ids[] = { + { .compatible = "mediatek,mt2701-mmsys", + .data = &mt2701_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, { } diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index f807621..98a9775 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -1215,6 +1215,7 @@ static int mtk_dsi_remove(struct platform_device *pdev) } static const struct of_device_id mtk_dsi_of_match[] = { + { .compatible = "mediatek,mt2701-dsi" }, { .compatible = "mediatek,mt8173-dsi" }, { }, }; diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index 34e95c6..944fb1d 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -467,11 +467,17 @@ static int mtk_mipi_tx_remove(struct platform_device *pdev) return 0; } +static const struct mtk_mipitx_data mt2701_mipitx_data = { + .data = (3 << 8) +}; + static const struct mtk_mipitx_data mt8173_mipitx_data = { .data = (0 << 8) }; static const struct of_device_id mtk_mipi_tx_match[] = { + { .compatible = "mediatek,mt2701-mipi-tx", + .data = &mt2701_mipitx_data }, { .compatible = "mediatek,mt8173-mipi-tx", .data = &mt8173_mipitx_data }, {}, -- 1.9.1