From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753807AbcIBL0E (ORCPT ); Fri, 2 Sep 2016 07:26:04 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:16808 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752151AbcIBL0A (ORCPT ); Fri, 2 Sep 2016 07:26:00 -0400 From: YT Shen To: , Philipp Zabel CC: David Airlie , Matthias Brugger , YT Shen , Daniel Kurtz , Mao Huang , CK Hu , Bibby Hsieh , Daniel Vetter , Thierry Reding , Jie Qiu , Maxime Ripard , Chris Wilson , shaoming chen , Jitao Shi , Boris Brezillon , Dan Carpenter , , , , , Sascha Hauer , , Subject: [PATCH v7 4/9] drm/mediatek: update display module connections Date: Fri, 2 Sep 2016 19:24:39 +0800 Message-ID: <1472815484-43821-5-git-send-email-yt.shen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org update connections for OVL, RDMA, BLS, DSI Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index b77d456..a9b209c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -32,6 +32,10 @@ #define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8 #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 + #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) @@ -71,6 +75,10 @@ #define DPI0_SEL_IN_RDMA1 0x1 #define COLOR1_SEL_IN_OVL1 0x1 +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define DSI_SEL_IN_BLS 0x0 + struct mtk_disp_mutex { int id; bool claimed; @@ -111,6 +119,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; value = OD_MOUT_EN_RDMA0; @@ -148,6 +159,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; } else { value = 0; } @@ -155,6 +169,15 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, return value; } +static void mtk_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); +} + void mtk_ddp_add_comp_to_path(void __iomem *config_regs, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) @@ -167,6 +190,8 @@ void mtk_ddp_add_comp_to_path(void __iomem *config_regs, writel_relaxed(reg, config_regs + addr); } + mtk_ddp_sout_sel(config_regs, cur, next); + value = mtk_ddp_sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) | value; -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: YT Shen Subject: [PATCH v7 4/9] drm/mediatek: update display module connections Date: Fri, 2 Sep 2016 19:24:39 +0800 Message-ID: <1472815484-43821-5-git-send-email-yt.shen@mediatek.com> References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org, Philipp Zabel Cc: Daniel Vetter , Jie Qiu , Mao Huang , yingjoe.chen@mediatek.com, Dan Carpenter , Jitao Shi , linux-mediatek@lists.infradead.org, Matthias Brugger , shaoming chen , linux-arm-kernel@lists.infradead.org, srv_heupstream@mediatek.com, emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Sascha Hauer , Maxime Ripard List-Id: linux-mediatek@lists.infradead.org dXBkYXRlIGNvbm5lY3Rpb25zIGZvciBPVkwsIFJETUEsIEJMUywgRFNJCgpTaWduZWQtb2ZmLWJ5 OiBZVCBTaGVuIDx5dC5zaGVuQG1lZGlhdGVrLmNvbT4KLS0tCiBkcml2ZXJzL2dwdS9kcm0vbWVk aWF0ZWsvbXRrX2RybV9kZHAuYyB8IDI1ICsrKysrKysrKysrKysrKysrKysrKysrKysKIDEgZmls ZSBjaGFuZ2VkLCAyNSBpbnNlcnRpb25zKCspCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJt L21lZGlhdGVrL210a19kcm1fZGRwLmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2Ry bV9kZHAuYwppbmRleCBiNzdkNDU2Li5hOWIyMDljIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9k cm0vbWVkaWF0ZWsvbXRrX2RybV9kZHAuYworKysgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsv bXRrX2RybV9kZHAuYwpAQCAtMzIsNiArMzIsMTAgQEAKICNkZWZpbmUgRElTUF9SRUdfQ09ORklH X0RJU1BfUkRNQTFfTU9VVF9FTgkweDBjOAogI2RlZmluZSBESVNQX1JFR19DT05GSUdfTU1TWVNf Q0dfQ09OMAkJMHgxMDAKIAorI2RlZmluZSBESVNQX1JFR19DT05GSUdfRElTUF9PVkxfTU9VVF9F TgkweDAzMAorI2RlZmluZSBESVNQX1JFR19DT05GSUdfT1VUX1NFTAkJCTB4MDRjCisjZGVmaW5l IERJU1BfUkVHX0NPTkZJR19EU0lfU0VMCQkJMHgwNTAKKwogI2RlZmluZSBESVNQX1JFR19NVVRF WF9FTihuKQkoMHgyMCArIDB4MjAgKiAobikpCiAjZGVmaW5lIERJU1BfUkVHX01VVEVYKG4pCSgw eDI0ICsgMHgyMCAqIChuKSkKICNkZWZpbmUgRElTUF9SRUdfTVVURVhfUlNUKG4pCSgweDI4ICsg MHgyMCAqIChuKSkKQEAgLTcxLDYgKzc1LDEwIEBACiAjZGVmaW5lIERQSTBfU0VMX0lOX1JETUEx CQkweDEKICNkZWZpbmUgQ09MT1IxX1NFTF9JTl9PVkwxCQkweDEKIAorI2RlZmluZSBPVkxfTU9V VF9FTl9SRE1BCQkweDEKKyNkZWZpbmUgQkxTX1RPX0RTSV9SRE1BMV9UT19EUEkxCTB4OAorI2Rl ZmluZSBEU0lfU0VMX0lOX0JMUwkJCTB4MAorCiBzdHJ1Y3QgbXRrX2Rpc3BfbXV0ZXggewogCWlu dCBpZDsKIAlib29sIGNsYWltZWQ7CkBAIC0xMTEsNiArMTE5LDkgQEAgc3RhdGljIHVuc2lnbmVk IGludCBtdGtfZGRwX21vdXRfZW4oZW51bSBtdGtfZGRwX2NvbXBfaWQgY3VyLAogCWlmIChjdXIg PT0gRERQX0NPTVBPTkVOVF9PVkwwICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9DT0xPUjApIHsK IAkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRElTUF9PVkwwX01PVVRfRU47CiAJCXZhbHVlID0g T1ZMMF9NT1VUX0VOX0NPTE9SMDsKKwl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX09W TDAgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX1JETUEwKSB7CisJCSphZGRyID0gRElTUF9SRUdf Q09ORklHX0RJU1BfT1ZMX01PVVRfRU47CisJCXZhbHVlID0gT1ZMX01PVVRfRU5fUkRNQTsKIAl9 IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX09EICYmIG5leHQgPT0gRERQX0NPTVBPTkVO VF9SRE1BMCkgewogCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX09EX01PVVRfRU47CiAJ CXZhbHVlID0gT0RfTU9VVF9FTl9SRE1BMDsKQEAgLTE0OCw2ICsxNTksOSBAQCBzdGF0aWMgdW5z aWduZWQgaW50IG10a19kZHBfc2VsX2luKGVudW0gbXRrX2RkcF9jb21wX2lkIGN1ciwKIAl9IGVs c2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX09WTDEgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5U X0NPTE9SMSkgewogCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX0NPTE9SMV9TRUxfSU47 CiAJCXZhbHVlID0gQ09MT1IxX1NFTF9JTl9PVkwxOworCX0gZWxzZSBpZiAoY3VyID09IEREUF9D T01QT05FTlRfQkxTICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EU0kwKSB7CisJCSphZGRyID0g RElTUF9SRUdfQ09ORklHX0RTSV9TRUw7CisJCXZhbHVlID0gRFNJX1NFTF9JTl9CTFM7CiAJfSBl bHNlIHsKIAkJdmFsdWUgPSAwOwogCX0KQEAgLTE1NSw2ICsxNjksMTUgQEAgc3RhdGljIHVuc2ln bmVkIGludCBtdGtfZGRwX3NlbF9pbihlbnVtIG10a19kZHBfY29tcF9pZCBjdXIsCiAJcmV0dXJu IHZhbHVlOwogfQogCitzdGF0aWMgdm9pZCBtdGtfZGRwX3NvdXRfc2VsKHZvaWQgX19pb21lbSAq Y29uZmlnX3JlZ3MsCisJCQkgICAgIGVudW0gbXRrX2RkcF9jb21wX2lkIGN1ciwKKwkJCSAgICAg ZW51bSBtdGtfZGRwX2NvbXBfaWQgbmV4dCkKK3sKKwlpZiAoY3VyID09IEREUF9DT01QT05FTlRf QkxTICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EU0kwKQorCQl3cml0ZWxfcmVsYXhlZChCTFNf VE9fRFNJX1JETUExX1RPX0RQSTEsCisJCQkgICAgICAgY29uZmlnX3JlZ3MgKyBESVNQX1JFR19D T05GSUdfT1VUX1NFTCk7Cit9CisKIHZvaWQgbXRrX2RkcF9hZGRfY29tcF90b19wYXRoKHZvaWQg X19pb21lbSAqY29uZmlnX3JlZ3MsCiAJCQkgICAgICBlbnVtIG10a19kZHBfY29tcF9pZCBjdXIs CiAJCQkgICAgICBlbnVtIG10a19kZHBfY29tcF9pZCBuZXh0KQpAQCAtMTY3LDYgKzE5MCw4IEBA IHZvaWQgbXRrX2RkcF9hZGRfY29tcF90b19wYXRoKHZvaWQgX19pb21lbSAqY29uZmlnX3JlZ3Ms CiAJCXdyaXRlbF9yZWxheGVkKHJlZywgY29uZmlnX3JlZ3MgKyBhZGRyKTsKIAl9CiAKKwltdGtf ZGRwX3NvdXRfc2VsKGNvbmZpZ19yZWdzLCBjdXIsIG5leHQpOworCiAJdmFsdWUgPSBtdGtfZGRw X3NlbF9pbihjdXIsIG5leHQsICZhZGRyKTsKIAlpZiAodmFsdWUpIHsKIAkJcmVnID0gcmVhZGxf cmVsYXhlZChjb25maWdfcmVncyArIGFkZHIpIHwgdmFsdWU7Ci0tIAoxLjkuMQoKX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcg bGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRl c2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: yt.shen@mediatek.com (YT Shen) Date: Fri, 2 Sep 2016 19:24:39 +0800 Subject: [PATCH v7 4/9] drm/mediatek: update display module connections In-Reply-To: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> Message-ID: <1472815484-43821-5-git-send-email-yt.shen@mediatek.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org update connections for OVL, RDMA, BLS, DSI Signed-off-by: YT Shen --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index b77d456..a9b209c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -32,6 +32,10 @@ #define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8 #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 + #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) @@ -71,6 +75,10 @@ #define DPI0_SEL_IN_RDMA1 0x1 #define COLOR1_SEL_IN_OVL1 0x1 +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define DSI_SEL_IN_BLS 0x0 + struct mtk_disp_mutex { int id; bool claimed; @@ -111,6 +119,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; value = OD_MOUT_EN_RDMA0; @@ -148,6 +159,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; } else { value = 0; } @@ -155,6 +169,15 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, return value; } +static void mtk_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); +} + void mtk_ddp_add_comp_to_path(void __iomem *config_regs, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) @@ -167,6 +190,8 @@ void mtk_ddp_add_comp_to_path(void __iomem *config_regs, writel_relaxed(reg, config_regs + addr); } + mtk_ddp_sout_sel(config_regs, cur, next); + value = mtk_ddp_sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) | value; -- 1.9.1