From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1753141AbcIBL1B (ORCPT <rfc822;w@1wt.eu>);
        Fri, 2 Sep 2016 07:27:01 -0400
Received: from mailgw02.mediatek.com ([210.61.82.184]:42438 "EHLO
        mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org
        with ESMTP id S1752690AbcIBL0R (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Fri, 2 Sep 2016 07:26:17 -0400
From: YT Shen <yt.shen@mediatek.com>
To: <dri-devel@lists.freedesktop.org>,
        Philipp Zabel <p.zabel@pengutronix.de>
CC: David Airlie <airlied@linux.ie>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        YT Shen <yt.shen@mediatek.com>, Daniel Kurtz <djkurtz@chromium.org>,
        Mao Huang <littlecvr@chromium.org>, CK Hu <ck.hu@mediatek.com>,
        Bibby Hsieh <bibby.hsieh@mediatek.com>,
        Daniel Vetter <daniel.vetter@ffwll.ch>,
        Thierry Reding <thierry.reding@gmail.com>,
        Jie Qiu <jie.qiu@mediatek.com>,
        Maxime Ripard <maxime.ripard@free-electrons.com>,
        Chris Wilson <chris@chris-wilson.co.uk>,
        shaoming chen <shaoming.chen@mediatek.com>,
        Jitao Shi <jitao.shi@mediatek.com>,
        Boris Brezillon <boris.brezillon@free-electrons.com>,
        Dan Carpenter <dan.carpenter@oracle.com>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-mediatek@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
        <srv_heupstream@mediatek.com>, Sascha Hauer <kernel@pengutronix.de>,
        <yingjoe.chen@mediatek.com>, <emil.l.velikov@gmail.com>
Subject: [PATCH v7 7/9] drm/mediatek: add dsi transfer function
Date: Fri, 2 Sep 2016 19:24:42 +0800
Message-ID: <1472815484-43821-8-git-send-email-yt.shen@mediatek.com>
X-Mailer: git-send-email 1.9.1
In-Reply-To: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com>
References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com>
MIME-Version: 1.0
Content-Type: text/plain
X-MTK: N
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

From: shaoming chen <shaoming.chen@mediatek.com>

add dsi read/write commands for transfer function

Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 188 +++++++++++++++++++++++++++++++++++++
 1 file changed, 188 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index d20f6f9..1103ff4 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -24,6 +24,7 @@
 #include <linux/of_graph.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
+#include <video/mipi_display.h>
 #include <video/videomode.h>
 
 #include "mtk_drm_ddp_comp.h"
@@ -81,8 +82,16 @@
 #define DSI_HBP_WC		0x54
 #define DSI_HFP_WC		0x58
 
+#define DSI_CMDQ_SIZE		0x60
+#define CMDQ_SIZE		0x3f
+
 #define DSI_HSTX_CKL_WC		0x64
 
+#define DSI_RX_DATA0		0x74
+#define DSI_RX_DATA1		0x78
+#define DSI_RX_DATA2		0x7c
+#define DSI_RX_DATA3		0x80
+
 #define DSI_RACK		0x84
 #define RACK				BIT(0)
 
@@ -118,8 +127,23 @@
 #define CLK_HS_POST			(0xff << 8)
 #define CLK_HS_EXIT			(0xff << 16)
 
+#define DSI_CMDQ0		0x180
+#define CONFIG				(0xff << 0)
+#define SHORT_PACKET			0
+#define LONG_PACKET			2
+#define BTA				BIT(2)
+#define DATA_ID				(0xff << 8)
+#define DATA_0				(0xff << 16)
+#define DATA_1				(0xff << 24)
+
 #define NS_TO_CYCLE(n, c)    ((n) / (c) + (((n) % (c)) ? 1 : 0))
 
+#define MTK_DSI_HOST_IS_READ(type) \
+	((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
+	(type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
+	(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
+	(type == MIPI_DSI_DCS_READ))
+
 struct phy;
 
 struct mtk_dsi {
@@ -465,6 +489,11 @@ static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
 	writel(inten, dsi->regs + DSI_INTEN);
 }
 
+static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
+{
+	dsi->irq_data &= ~irq_bit;
+}
+
 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
 {
 	dsi->irq_data |= irq_bit;
@@ -788,9 +817,168 @@ static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
 	return 0;
 }
 
+static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
+{
+	u32 timeout_ms = 500000; /* total 1s ~ 2s timeout */
+
+	while (timeout_ms--) {
+		if (!(readl(dsi->regs + DSI_INTSTA) & DSI_BUSY))
+			break;
+
+		usleep_range(2, 4);
+	}
+
+	if (timeout_ms == 0) {
+		dev_info(dsi->dev, "polling dsi wait not busy timeout!\n");
+
+		mtk_dsi_enable(dsi);
+		mtk_dsi_reset_engine(dsi);
+	}
+}
+
+static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
+				     unsigned int timeout)
+{
+	s32 ret = 0;
+	unsigned long jiffies = msecs_to_jiffies(timeout);
+
+	ret = wait_event_interruptible_timeout(_dsi_irq_wait_queue,
+					       dsi->irq_data & irq_flag,
+					       jiffies);
+	if (ret == 0) {
+		dev_info(dsi->dev, "Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
+
+		mtk_dsi_enable(dsi);
+		mtk_dsi_reset_engine(dsi);
+	}
+
+	return ret;
+}
+
+static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
+{
+	switch (type) {
+	case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
+	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
+		return 1;
+	case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
+	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
+		return 2;
+	case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
+	case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
+		return read_data[1] + read_data[2] * 16;
+	case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
+		DRM_INFO("type is 0x02, try again\n");
+		break;
+	default:
+		DRM_INFO("type(0x%x) cannot be non-recognite\n", type);
+		break;
+	}
+
+	return 0;
+}
+
+static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
+{
+	const char *tx_buf = msg->tx_buf;
+	u8 config, cmdq_size, cmdq_off, type = msg->type;
+	u32 reg_val, cmdq_mask, i;
+
+	if (MTK_DSI_HOST_IS_READ(type))
+		config = BTA;
+	else
+		config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
+
+	if (msg->tx_len > 2) {
+		cmdq_size = 1 + (msg->tx_len + 3) / 4;
+		cmdq_off = 4;
+		cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
+		reg_val = (msg->tx_len << 16) | (type << 8) | config;
+	} else {
+		cmdq_size = 1;
+		cmdq_off = 2;
+		cmdq_mask = CONFIG | DATA_ID;
+		reg_val = (type << 8) | config;
+	}
+
+	for (i = 0; i < msg->tx_len; i++)
+		writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
+
+	mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
+	mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
+}
+
+static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
+				     const struct mipi_dsi_msg *msg, u8 flag)
+{
+	mtk_dsi_wait_for_idle(dsi);
+	mtk_dsi_irq_data_clear(dsi, flag);
+	mtk_dsi_cmdq(dsi, msg);
+	mtk_dsi_start(dsi);
+
+	if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
+		return -1;
+	else
+		return 0;
+}
+
+static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
+				     const struct mipi_dsi_msg *msg)
+{
+	struct mtk_dsi *dsi = host_to_dsi(host);
+	u32 recv_cnt, i;
+	u8 read_data[16];
+	void *src_addr;
+	u8 irq_flag = CMD_DONE_INT_FLAG;
+
+	if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
+		dev_info(dsi->dev, "dsi engine is not command mode\n");
+		return -1;
+	}
+
+	if (MTK_DSI_HOST_IS_READ(msg->type))
+		irq_flag |= LPRX_RD_RDY_INT_FLAG;
+
+	if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
+		return -1;
+
+	if (!MTK_DSI_HOST_IS_READ(msg->type))
+		return 0;
+
+	if (!msg->rx_buf) {
+		dev_info(dsi->dev, "dsi receive buffer size may be NULL\n");
+		return -1;
+	}
+
+	for (i = 0; i < 16; i++)
+		*(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
+
+	recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
+
+	if (recv_cnt > 2)
+		src_addr = &read_data[4];
+	else
+		src_addr = &read_data[1];
+
+	if (recv_cnt > 10)
+		recv_cnt = 10;
+
+	if (recv_cnt > msg->rx_len)
+		recv_cnt = msg->rx_len;
+
+	if (recv_cnt)
+		memcpy(msg->rx_buf, src_addr, recv_cnt);
+
+	dev_info(dsi->dev, "dsi get %d byte data from the panel address(0x%x)\n",
+		 recv_cnt, *((u8 *)(msg->tx_buf)));
+
+	return recv_cnt;
+}
+
 static const struct mipi_dsi_host_ops mtk_dsi_ops = {
 	.attach = mtk_dsi_host_attach,
 	.detach = mtk_dsi_host_detach,
+	.transfer = mtk_dsi_host_transfer,
 };
 
 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
-- 
1.9.1

From mboxrd@z Thu Jan  1 00:00:00 1970
From: YT Shen <yt.shen@mediatek.com>
Subject: [PATCH v7 7/9] drm/mediatek: add dsi transfer function
Date: Fri, 2 Sep 2016 19:24:42 +0800
Message-ID: <1472815484-43821-8-git-send-email-yt.shen@mediatek.com>
References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
Return-path: <dri-devel-bounces@lists.freedesktop.org>
In-Reply-To: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com>
List-Unsubscribe: <https://lists.freedesktop.org/mailman/options/dri-devel>,
 <mailto:dri-devel-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <https://lists.freedesktop.org/archives/dri-devel>
List-Post: <mailto:dri-devel@lists.freedesktop.org>
List-Help: <mailto:dri-devel-request@lists.freedesktop.org?subject=help>
List-Subscribe: <https://lists.freedesktop.org/mailman/listinfo/dri-devel>,
 <mailto:dri-devel-request@lists.freedesktop.org?subject=subscribe>
Errors-To: dri-devel-bounces@lists.freedesktop.org
Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org>
To: dri-devel@lists.freedesktop.org, Philipp Zabel <p.zabel@pengutronix.de>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Jie Qiu <jie.qiu@mediatek.com>, Mao Huang <littlecvr@chromium.org>, yingjoe.chen@mediatek.com, Dan Carpenter <dan.carpenter@oracle.com>, Jitao Shi <jitao.shi@mediatek.com>, linux-mediatek@lists.infradead.org, Matthias Brugger <matthias.bgg@gmail.com>, shaoming chen <shaoming.chen@mediatek.com>, linux-arm-kernel@lists.infradead.org, srv_heupstream@mediatek.com, emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Sascha Hauer <kernel@pengutronix.de>, Maxime Ripard <maxime.ripard@free-electrons.com>
List-Id: linux-mediatek@lists.infradead.org

RnJvbTogc2hhb21pbmcgY2hlbiA8c2hhb21pbmcuY2hlbkBtZWRpYXRlay5jb20+CgphZGQgZHNp
IHJlYWQvd3JpdGUgY29tbWFuZHMgZm9yIHRyYW5zZmVyIGZ1bmN0aW9uCgpTaWduZWQtb2ZmLWJ5
OiBzaGFvbWluZyBjaGVuIDxzaGFvbWluZy5jaGVuQG1lZGlhdGVrLmNvbT4KLS0tCiBkcml2ZXJz
L2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RzaS5jIHwgMTg4ICsrKysrKysrKysrKysrKysrKysrKysr
KysrKysrKysrKysrKysKIDEgZmlsZSBjaGFuZ2VkLCAxODggaW5zZXJ0aW9ucygrKQoKZGlmZiAt
LWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHNpLmMgYi9kcml2ZXJzL2dwdS9k
cm0vbWVkaWF0ZWsvbXRrX2RzaS5jCmluZGV4IGQyMGY2ZjkuLjExMDNmZjQgMTAwNjQ0Ci0tLSBh
L2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHNpLmMKKysrIGIvZHJpdmVycy9ncHUvZHJt
L21lZGlhdGVrL210a19kc2kuYwpAQCAtMjQsNiArMjQsNyBAQAogI2luY2x1ZGUgPGxpbnV4L29m
X2dyYXBoLmg+CiAjaW5jbHVkZSA8bGludXgvcGh5L3BoeS5oPgogI2luY2x1ZGUgPGxpbnV4L3Bs
YXRmb3JtX2RldmljZS5oPgorI2luY2x1ZGUgPHZpZGVvL21pcGlfZGlzcGxheS5oPgogI2luY2x1
ZGUgPHZpZGVvL3ZpZGVvbW9kZS5oPgogCiAjaW5jbHVkZSAibXRrX2RybV9kZHBfY29tcC5oIgpA
QCAtODEsOCArODIsMTYgQEAKICNkZWZpbmUgRFNJX0hCUF9XQwkJMHg1NAogI2RlZmluZSBEU0lf
SEZQX1dDCQkweDU4CiAKKyNkZWZpbmUgRFNJX0NNRFFfU0laRQkJMHg2MAorI2RlZmluZSBDTURR
X1NJWkUJCTB4M2YKKwogI2RlZmluZSBEU0lfSFNUWF9DS0xfV0MJCTB4NjQKIAorI2RlZmluZSBE
U0lfUlhfREFUQTAJCTB4NzQKKyNkZWZpbmUgRFNJX1JYX0RBVEExCQkweDc4CisjZGVmaW5lIERT
SV9SWF9EQVRBMgkJMHg3YworI2RlZmluZSBEU0lfUlhfREFUQTMJCTB4ODAKKwogI2RlZmluZSBE
U0lfUkFDSwkJMHg4NAogI2RlZmluZSBSQUNLCQkJCUJJVCgwKQogCkBAIC0xMTgsOCArMTI3LDIz
IEBACiAjZGVmaW5lIENMS19IU19QT1NUCQkJKDB4ZmYgPDwgOCkKICNkZWZpbmUgQ0xLX0hTX0VY
SVQJCQkoMHhmZiA8PCAxNikKIAorI2RlZmluZSBEU0lfQ01EUTAJCTB4MTgwCisjZGVmaW5lIENP
TkZJRwkJCQkoMHhmZiA8PCAwKQorI2RlZmluZSBTSE9SVF9QQUNLRVQJCQkwCisjZGVmaW5lIExP
TkdfUEFDS0VUCQkJMgorI2RlZmluZSBCVEEJCQkJQklUKDIpCisjZGVmaW5lIERBVEFfSUQJCQkJ
KDB4ZmYgPDwgOCkKKyNkZWZpbmUgREFUQV8wCQkJCSgweGZmIDw8IDE2KQorI2RlZmluZSBEQVRB
XzEJCQkJKDB4ZmYgPDwgMjQpCisKICNkZWZpbmUgTlNfVE9fQ1lDTEUobiwgYykgICAgKChuKSAv
IChjKSArICgoKG4pICUgKGMpKSA/IDEgOiAwKSkKIAorI2RlZmluZSBNVEtfRFNJX0hPU1RfSVNf
UkVBRCh0eXBlKSBcCisJKCh0eXBlID09IE1JUElfRFNJX0dFTkVSSUNfUkVBRF9SRVFVRVNUXzBf
UEFSQU0pIHx8IFwKKwkodHlwZSA9PSBNSVBJX0RTSV9HRU5FUklDX1JFQURfUkVRVUVTVF8xX1BB
UkFNKSB8fCBcCisJKHR5cGUgPT0gTUlQSV9EU0lfR0VORVJJQ19SRUFEX1JFUVVFU1RfMl9QQVJB
TSkgfHwgXAorCSh0eXBlID09IE1JUElfRFNJX0RDU19SRUFEKSkKKwogc3RydWN0IHBoeTsKIAog
c3RydWN0IG10a19kc2kgewpAQCAtNDY1LDYgKzQ4OSwxMSBAQCBzdGF0aWMgdm9pZCBtdGtfZHNp
X3NldF9pbnRlcnJ1cHRfZW5hYmxlKHN0cnVjdCBtdGtfZHNpICpkc2kpCiAJd3JpdGVsKGludGVu
LCBkc2ktPnJlZ3MgKyBEU0lfSU5URU4pOwogfQogCitzdGF0aWMgdm9pZCBtdGtfZHNpX2lycV9k
YXRhX2NsZWFyKHN0cnVjdCBtdGtfZHNpICpkc2ksIHUzMiBpcnFfYml0KQoreworCWRzaS0+aXJx
X2RhdGEgJj0gfmlycV9iaXQ7Cit9CisKIHN0YXRpYyB2b2lkIG10a19kc2lfaXJxX2RhdGFfc2V0
KHN0cnVjdCBtdGtfZHNpICpkc2ksIHUzMiBpcnFfYml0KQogewogCWRzaS0+aXJxX2RhdGEgfD0g
aXJxX2JpdDsKQEAgLTc4OCw5ICs4MTcsMTY4IEBAIHN0YXRpYyBpbnQgbXRrX2RzaV9ob3N0X2Rl
dGFjaChzdHJ1Y3QgbWlwaV9kc2lfaG9zdCAqaG9zdCwKIAlyZXR1cm4gMDsKIH0KIAorc3RhdGlj
IHZvaWQgbXRrX2RzaV93YWl0X2Zvcl9pZGxlKHN0cnVjdCBtdGtfZHNpICpkc2kpCit7CisJdTMy
IHRpbWVvdXRfbXMgPSA1MDAwMDA7IC8qIHRvdGFsIDFzIH4gMnMgdGltZW91dCAqLworCisJd2hp
bGUgKHRpbWVvdXRfbXMtLSkgeworCQlpZiAoIShyZWFkbChkc2ktPnJlZ3MgKyBEU0lfSU5UU1RB
KSAmIERTSV9CVVNZKSkKKwkJCWJyZWFrOworCisJCXVzbGVlcF9yYW5nZSgyLCA0KTsKKwl9CisK
KwlpZiAodGltZW91dF9tcyA9PSAwKSB7CisJCWRldl9pbmZvKGRzaS0+ZGV2LCAicG9sbGluZyBk
c2kgd2FpdCBub3QgYnVzeSB0aW1lb3V0IVxuIik7CisKKwkJbXRrX2RzaV9lbmFibGUoZHNpKTsK
KwkJbXRrX2RzaV9yZXNldF9lbmdpbmUoZHNpKTsKKwl9Cit9CisKK3N0YXRpYyBzMzIgbXRrX2Rz
aV93YWl0X2Zvcl9pcnFfZG9uZShzdHJ1Y3QgbXRrX2RzaSAqZHNpLCB1MzIgaXJxX2ZsYWcsCisJ
CQkJICAgICB1bnNpZ25lZCBpbnQgdGltZW91dCkKK3sKKwlzMzIgcmV0ID0gMDsKKwl1bnNpZ25l
ZCBsb25nIGppZmZpZXMgPSBtc2Vjc190b19qaWZmaWVzKHRpbWVvdXQpOworCisJcmV0ID0gd2Fp
dF9ldmVudF9pbnRlcnJ1cHRpYmxlX3RpbWVvdXQoX2RzaV9pcnFfd2FpdF9xdWV1ZSwKKwkJCQkJ
ICAgICAgIGRzaS0+aXJxX2RhdGEgJiBpcnFfZmxhZywKKwkJCQkJICAgICAgIGppZmZpZXMpOwor
CWlmIChyZXQgPT0gMCkgeworCQlkZXZfaW5mbyhkc2ktPmRldiwgIldhaXQgRFNJIElSUSgweCUw
OHgpIFRpbWVvdXRcbiIsIGlycV9mbGFnKTsKKworCQltdGtfZHNpX2VuYWJsZShkc2kpOworCQlt
dGtfZHNpX3Jlc2V0X2VuZ2luZShkc2kpOworCX0KKworCXJldHVybiByZXQ7Cit9CisKK3N0YXRp
YyB1MzIgbXRrX2RzaV9yZWN2X2NudCh1OCB0eXBlLCB1OCAqcmVhZF9kYXRhKQoreworCXN3aXRj
aCAodHlwZSkgeworCWNhc2UgTUlQSV9EU0lfUlhfR0VORVJJQ19TSE9SVF9SRUFEX1JFU1BPTlNF
XzFCWVRFOgorCWNhc2UgTUlQSV9EU0lfUlhfRENTX1NIT1JUX1JFQURfUkVTUE9OU0VfMUJZVEU6
CisJCXJldHVybiAxOworCWNhc2UgTUlQSV9EU0lfUlhfR0VORVJJQ19TSE9SVF9SRUFEX1JFU1BP
TlNFXzJCWVRFOgorCWNhc2UgTUlQSV9EU0lfUlhfRENTX1NIT1JUX1JFQURfUkVTUE9OU0VfMkJZ
VEU6CisJCXJldHVybiAyOworCWNhc2UgTUlQSV9EU0lfUlhfR0VORVJJQ19MT05HX1JFQURfUkVT
UE9OU0U6CisJY2FzZSBNSVBJX0RTSV9SWF9EQ1NfTE9OR19SRUFEX1JFU1BPTlNFOgorCQlyZXR1
cm4gcmVhZF9kYXRhWzFdICsgcmVhZF9kYXRhWzJdICogMTY7CisJY2FzZSBNSVBJX0RTSV9SWF9B
Q0tOT1dMRURHRV9BTkRfRVJST1JfUkVQT1JUOgorCQlEUk1fSU5GTygidHlwZSBpcyAweDAyLCB0
cnkgYWdhaW5cbiIpOworCQlicmVhazsKKwlkZWZhdWx0OgorCQlEUk1fSU5GTygidHlwZSgweCV4
KSBjYW5ub3QgYmUgbm9uLXJlY29nbml0ZVxuIiwgdHlwZSk7CisJCWJyZWFrOworCX0KKworCXJl
dHVybiAwOworfQorCitzdGF0aWMgdm9pZCBtdGtfZHNpX2NtZHEoc3RydWN0IG10a19kc2kgKmRz
aSwgY29uc3Qgc3RydWN0IG1pcGlfZHNpX21zZyAqbXNnKQoreworCWNvbnN0IGNoYXIgKnR4X2J1
ZiA9IG1zZy0+dHhfYnVmOworCXU4IGNvbmZpZywgY21kcV9zaXplLCBjbWRxX29mZiwgdHlwZSA9
IG1zZy0+dHlwZTsKKwl1MzIgcmVnX3ZhbCwgY21kcV9tYXNrLCBpOworCisJaWYgKE1US19EU0lf
SE9TVF9JU19SRUFEKHR5cGUpKQorCQljb25maWcgPSBCVEE7CisJZWxzZQorCQljb25maWcgPSAo
bXNnLT50eF9sZW4gPiAyKSA/IExPTkdfUEFDS0VUIDogU0hPUlRfUEFDS0VUOworCisJaWYgKG1z
Zy0+dHhfbGVuID4gMikgeworCQljbWRxX3NpemUgPSAxICsgKG1zZy0+dHhfbGVuICsgMykgLyA0
OworCQljbWRxX29mZiA9IDQ7CisJCWNtZHFfbWFzayA9IENPTkZJRyB8IERBVEFfSUQgfCBEQVRB
XzAgfCBEQVRBXzE7CisJCXJlZ192YWwgPSAobXNnLT50eF9sZW4gPDwgMTYpIHwgKHR5cGUgPDwg
OCkgfCBjb25maWc7CisJfSBlbHNlIHsKKwkJY21kcV9zaXplID0gMTsKKwkJY21kcV9vZmYgPSAy
OworCQljbWRxX21hc2sgPSBDT05GSUcgfCBEQVRBX0lEOworCQlyZWdfdmFsID0gKHR5cGUgPDwg
OCkgfCBjb25maWc7CisJfQorCisJZm9yIChpID0gMDsgaSA8IG1zZy0+dHhfbGVuOyBpKyspCisJ
CXdyaXRlYih0eF9idWZbaV0sIGRzaS0+cmVncyArIERTSV9DTURRMCArIGNtZHFfb2ZmICsgaSk7
CisKKwltdGtfZHNpX21hc2soZHNpLCBEU0lfQ01EUTAsIGNtZHFfbWFzaywgcmVnX3ZhbCk7CisJ
bXRrX2RzaV9tYXNrKGRzaSwgRFNJX0NNRFFfU0laRSwgQ01EUV9TSVpFLCBjbWRxX3NpemUpOwor
fQorCitzdGF0aWMgc3NpemVfdCBtdGtfZHNpX2hvc3Rfc2VuZF9jbWQoc3RydWN0IG10a19kc2kg
KmRzaSwKKwkJCQkgICAgIGNvbnN0IHN0cnVjdCBtaXBpX2RzaV9tc2cgKm1zZywgdTggZmxhZykK
K3sKKwltdGtfZHNpX3dhaXRfZm9yX2lkbGUoZHNpKTsKKwltdGtfZHNpX2lycV9kYXRhX2NsZWFy
KGRzaSwgZmxhZyk7CisJbXRrX2RzaV9jbWRxKGRzaSwgbXNnKTsKKwltdGtfZHNpX3N0YXJ0KGRz
aSk7CisKKwlpZiAoIW10a19kc2lfd2FpdF9mb3JfaXJxX2RvbmUoZHNpLCBmbGFnLCAyMDAwKSkK
KwkJcmV0dXJuIC0xOworCWVsc2UKKwkJcmV0dXJuIDA7Cit9CisKK3N0YXRpYyBzc2l6ZV90IG10
a19kc2lfaG9zdF90cmFuc2ZlcihzdHJ1Y3QgbWlwaV9kc2lfaG9zdCAqaG9zdCwKKwkJCQkgICAg
IGNvbnN0IHN0cnVjdCBtaXBpX2RzaV9tc2cgKm1zZykKK3sKKwlzdHJ1Y3QgbXRrX2RzaSAqZHNp
ID0gaG9zdF90b19kc2koaG9zdCk7CisJdTMyIHJlY3ZfY250LCBpOworCXU4IHJlYWRfZGF0YVsx
Nl07CisJdm9pZCAqc3JjX2FkZHI7CisJdTggaXJxX2ZsYWcgPSBDTURfRE9ORV9JTlRfRkxBRzsK
KworCWlmIChyZWFkbChkc2ktPnJlZ3MgKyBEU0lfTU9ERV9DVFJMKSAmIE1PREUpIHsKKwkJZGV2
X2luZm8oZHNpLT5kZXYsICJkc2kgZW5naW5lIGlzIG5vdCBjb21tYW5kIG1vZGVcbiIpOworCQly
ZXR1cm4gLTE7CisJfQorCisJaWYgKE1US19EU0lfSE9TVF9JU19SRUFEKG1zZy0+dHlwZSkpCisJ
CWlycV9mbGFnIHw9IExQUlhfUkRfUkRZX0lOVF9GTEFHOworCisJaWYgKG10a19kc2lfaG9zdF9z
ZW5kX2NtZChkc2ksIG1zZywgaXJxX2ZsYWcpIDwgMCkKKwkJcmV0dXJuIC0xOworCisJaWYgKCFN
VEtfRFNJX0hPU1RfSVNfUkVBRChtc2ctPnR5cGUpKQorCQlyZXR1cm4gMDsKKworCWlmICghbXNn
LT5yeF9idWYpIHsKKwkJZGV2X2luZm8oZHNpLT5kZXYsICJkc2kgcmVjZWl2ZSBidWZmZXIgc2l6
ZSBtYXkgYmUgTlVMTFxuIik7CisJCXJldHVybiAtMTsKKwl9CisKKwlmb3IgKGkgPSAwOyBpIDwg
MTY7IGkrKykKKwkJKihyZWFkX2RhdGEgKyBpKSA9IHJlYWRiKGRzaS0+cmVncyArIERTSV9SWF9E
QVRBMCArIGkpOworCisJcmVjdl9jbnQgPSBtdGtfZHNpX3JlY3ZfY250KHJlYWRfZGF0YVswXSwg
cmVhZF9kYXRhKTsKKworCWlmIChyZWN2X2NudCA+IDIpCisJCXNyY19hZGRyID0gJnJlYWRfZGF0
YVs0XTsKKwllbHNlCisJCXNyY19hZGRyID0gJnJlYWRfZGF0YVsxXTsKKworCWlmIChyZWN2X2Nu
dCA+IDEwKQorCQlyZWN2X2NudCA9IDEwOworCisJaWYgKHJlY3ZfY250ID4gbXNnLT5yeF9sZW4p
CisJCXJlY3ZfY250ID0gbXNnLT5yeF9sZW47CisKKwlpZiAocmVjdl9jbnQpCisJCW1lbWNweSht
c2ctPnJ4X2J1Ziwgc3JjX2FkZHIsIHJlY3ZfY250KTsKKworCWRldl9pbmZvKGRzaS0+ZGV2LCAi
ZHNpIGdldCAlZCBieXRlIGRhdGEgZnJvbSB0aGUgcGFuZWwgYWRkcmVzcygweCV4KVxuIiwKKwkJ
IHJlY3ZfY250LCAqKCh1OCAqKShtc2ctPnR4X2J1ZikpKTsKKworCXJldHVybiByZWN2X2NudDsK
K30KKwogc3RhdGljIGNvbnN0IHN0cnVjdCBtaXBpX2RzaV9ob3N0X29wcyBtdGtfZHNpX29wcyA9
IHsKIAkuYXR0YWNoID0gbXRrX2RzaV9ob3N0X2F0dGFjaCwKIAkuZGV0YWNoID0gbXRrX2RzaV9o
b3N0X2RldGFjaCwKKwkudHJhbnNmZXIgPSBtdGtfZHNpX2hvc3RfdHJhbnNmZXIsCiB9OwogCiBz
dGF0aWMgaW50IG10a19kc2lfYmluZChzdHJ1Y3QgZGV2aWNlICpkZXYsIHN0cnVjdCBkZXZpY2Ug
Km1hc3Rlciwgdm9pZCAqZGF0YSkKLS0gCjEuOS4xCgpfX19fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBs
aXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1h
bi9saXN0aW5mby9kcmktZGV2ZWwK

From mboxrd@z Thu Jan  1 00:00:00 1970
From: yt.shen@mediatek.com (YT Shen)
Date: Fri, 2 Sep 2016 19:24:42 +0800
Subject: [PATCH v7 7/9] drm/mediatek: add dsi transfer function
In-Reply-To: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com>
References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com>
Message-ID: <1472815484-43821-8-git-send-email-yt.shen@mediatek.com>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

From: shaoming chen <shaoming.chen@mediatek.com>

add dsi read/write commands for transfer function

Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 188 +++++++++++++++++++++++++++++++++++++
 1 file changed, 188 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index d20f6f9..1103ff4 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -24,6 +24,7 @@
 #include <linux/of_graph.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
+#include <video/mipi_display.h>
 #include <video/videomode.h>
 
 #include "mtk_drm_ddp_comp.h"
@@ -81,8 +82,16 @@
 #define DSI_HBP_WC		0x54
 #define DSI_HFP_WC		0x58
 
+#define DSI_CMDQ_SIZE		0x60
+#define CMDQ_SIZE		0x3f
+
 #define DSI_HSTX_CKL_WC		0x64
 
+#define DSI_RX_DATA0		0x74
+#define DSI_RX_DATA1		0x78
+#define DSI_RX_DATA2		0x7c
+#define DSI_RX_DATA3		0x80
+
 #define DSI_RACK		0x84
 #define RACK				BIT(0)
 
@@ -118,8 +127,23 @@
 #define CLK_HS_POST			(0xff << 8)
 #define CLK_HS_EXIT			(0xff << 16)
 
+#define DSI_CMDQ0		0x180
+#define CONFIG				(0xff << 0)
+#define SHORT_PACKET			0
+#define LONG_PACKET			2
+#define BTA				BIT(2)
+#define DATA_ID				(0xff << 8)
+#define DATA_0				(0xff << 16)
+#define DATA_1				(0xff << 24)
+
 #define NS_TO_CYCLE(n, c)    ((n) / (c) + (((n) % (c)) ? 1 : 0))
 
+#define MTK_DSI_HOST_IS_READ(type) \
+	((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
+	(type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
+	(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
+	(type == MIPI_DSI_DCS_READ))
+
 struct phy;
 
 struct mtk_dsi {
@@ -465,6 +489,11 @@ static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
 	writel(inten, dsi->regs + DSI_INTEN);
 }
 
+static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
+{
+	dsi->irq_data &= ~irq_bit;
+}
+
 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
 {
 	dsi->irq_data |= irq_bit;
@@ -788,9 +817,168 @@ static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
 	return 0;
 }
 
+static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
+{
+	u32 timeout_ms = 500000; /* total 1s ~ 2s timeout */
+
+	while (timeout_ms--) {
+		if (!(readl(dsi->regs + DSI_INTSTA) & DSI_BUSY))
+			break;
+
+		usleep_range(2, 4);
+	}
+
+	if (timeout_ms == 0) {
+		dev_info(dsi->dev, "polling dsi wait not busy timeout!\n");
+
+		mtk_dsi_enable(dsi);
+		mtk_dsi_reset_engine(dsi);
+	}
+}
+
+static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
+				     unsigned int timeout)
+{
+	s32 ret = 0;
+	unsigned long jiffies = msecs_to_jiffies(timeout);
+
+	ret = wait_event_interruptible_timeout(_dsi_irq_wait_queue,
+					       dsi->irq_data & irq_flag,
+					       jiffies);
+	if (ret == 0) {
+		dev_info(dsi->dev, "Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
+
+		mtk_dsi_enable(dsi);
+		mtk_dsi_reset_engine(dsi);
+	}
+
+	return ret;
+}
+
+static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
+{
+	switch (type) {
+	case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
+	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
+		return 1;
+	case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
+	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
+		return 2;
+	case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
+	case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
+		return read_data[1] + read_data[2] * 16;
+	case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
+		DRM_INFO("type is 0x02, try again\n");
+		break;
+	default:
+		DRM_INFO("type(0x%x) cannot be non-recognite\n", type);
+		break;
+	}
+
+	return 0;
+}
+
+static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
+{
+	const char *tx_buf = msg->tx_buf;
+	u8 config, cmdq_size, cmdq_off, type = msg->type;
+	u32 reg_val, cmdq_mask, i;
+
+	if (MTK_DSI_HOST_IS_READ(type))
+		config = BTA;
+	else
+		config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
+
+	if (msg->tx_len > 2) {
+		cmdq_size = 1 + (msg->tx_len + 3) / 4;
+		cmdq_off = 4;
+		cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
+		reg_val = (msg->tx_len << 16) | (type << 8) | config;
+	} else {
+		cmdq_size = 1;
+		cmdq_off = 2;
+		cmdq_mask = CONFIG | DATA_ID;
+		reg_val = (type << 8) | config;
+	}
+
+	for (i = 0; i < msg->tx_len; i++)
+		writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
+
+	mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
+	mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
+}
+
+static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
+				     const struct mipi_dsi_msg *msg, u8 flag)
+{
+	mtk_dsi_wait_for_idle(dsi);
+	mtk_dsi_irq_data_clear(dsi, flag);
+	mtk_dsi_cmdq(dsi, msg);
+	mtk_dsi_start(dsi);
+
+	if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
+		return -1;
+	else
+		return 0;
+}
+
+static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
+				     const struct mipi_dsi_msg *msg)
+{
+	struct mtk_dsi *dsi = host_to_dsi(host);
+	u32 recv_cnt, i;
+	u8 read_data[16];
+	void *src_addr;
+	u8 irq_flag = CMD_DONE_INT_FLAG;
+
+	if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
+		dev_info(dsi->dev, "dsi engine is not command mode\n");
+		return -1;
+	}
+
+	if (MTK_DSI_HOST_IS_READ(msg->type))
+		irq_flag |= LPRX_RD_RDY_INT_FLAG;
+
+	if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
+		return -1;
+
+	if (!MTK_DSI_HOST_IS_READ(msg->type))
+		return 0;
+
+	if (!msg->rx_buf) {
+		dev_info(dsi->dev, "dsi receive buffer size may be NULL\n");
+		return -1;
+	}
+
+	for (i = 0; i < 16; i++)
+		*(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
+
+	recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
+
+	if (recv_cnt > 2)
+		src_addr = &read_data[4];
+	else
+		src_addr = &read_data[1];
+
+	if (recv_cnt > 10)
+		recv_cnt = 10;
+
+	if (recv_cnt > msg->rx_len)
+		recv_cnt = msg->rx_len;
+
+	if (recv_cnt)
+		memcpy(msg->rx_buf, src_addr, recv_cnt);
+
+	dev_info(dsi->dev, "dsi get %d byte data from the panel address(0x%x)\n",
+		 recv_cnt, *((u8 *)(msg->tx_buf)));
+
+	return recv_cnt;
+}
+
 static const struct mipi_dsi_host_ops mtk_dsi_ops = {
 	.attach = mtk_dsi_host_attach,
 	.detach = mtk_dsi_host_detach,
+	.transfer = mtk_dsi_host_transfer,
 };
 
 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
-- 
1.9.1