From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51600) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bgHjz-0008DX-VO for qemu-devel@nongnu.org; Sat, 03 Sep 2016 16:40:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bgHju-00035S-58 for qemu-devel@nongnu.org; Sat, 03 Sep 2016 16:40:38 -0400 Received: from mail-pa0-x243.google.com ([2607:f8b0:400e:c03::243]:33567) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bgHjt-00035K-UG for qemu-devel@nongnu.org; Sat, 03 Sep 2016 16:40:34 -0400 Received: by mail-pa0-x243.google.com with SMTP id vy10so7115863pac.0 for ; Sat, 03 Sep 2016 13:40:33 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Sat, 3 Sep 2016 13:39:56 -0700 Message-Id: <1472935202-3342-29-git-send-email-rth@twiddle.net> In-Reply-To: <1472935202-3342-1-git-send-email-rth@twiddle.net> References: <1472935202-3342-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v3 28/34] target-arm: emulate SWP with atomic_xchg helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Emilio G. Cota" From: "Emilio G. Cota" Signed-off-by: Emilio G. Cota Message-Id: <1467054136-10430-25-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson --- target-arm/translate.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 680635c..2b3c34f 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -8741,25 +8741,26 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } tcg_temp_free_i32(addr); } else { + TCGv taddr; + TCGMemOp opc = s->be_data; + /* SWP instruction */ rm = (insn) & 0xf; - /* ??? This is not really atomic. However we know - we never have multiple CPUs running in parallel, - so it is good enough. */ - addr = load_reg(s, rn); - tmp = load_reg(s, rm); - tmp2 = tcg_temp_new_i32(); if (insn & (1 << 22)) { - gen_aa32_ld8u(s, tmp2, addr, get_mem_index(s)); - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); + opc |= MO_UB; } else { - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + opc |= MO_UL | MO_ALIGN; } - tcg_temp_free_i32(tmp); + + addr = load_reg(s, rn); + taddr = gen_aa32_addr(s, addr, opc); tcg_temp_free_i32(addr); - store_reg(s, rd, tmp2); + + tmp = load_reg(s, rm); + tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, + get_mem_index(s), opc); + store_reg(s, rd, tmp); } } } else { -- 2.7.4