[PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

[PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

[Randy Li]

changelog:
v7
  Some minor fixup
v6
  Send the last two patches
v5
  A few modification at style, add the missing doc in the last 
  commit.
v4
  1. Adding the reset callback in struct phy_ops.
  2. Moving the reset into phy rockchip usb.
  3. Trying to call a reset when dwc2 wakeup in rk3288.
v3
 Rebased from previous commit.

Randy Li (4):
  phy: Add reset callback
  phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
    wakeup
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 .../devicetree/bindings/phy/rockchip-usb-phy.txt     |  3 +++
 arch/arm/boot/dts/rk3288.dtsi                        |  4 ++++
 drivers/phy/phy-rockchip-usb.c                       | 20 ++++++++++++++++++++
 drivers/usb/dwc2/core_intr.c                         | 12 ++++++++++++
 include/linux/phy/phy.h                              |  2 ++
 5 files changed, 41 insertions(+)

-- 
2.7.4

[PATCH v7 0/4] the fix for the USB HOST1 at rk3288 platform

[Randy Li]

changelog:
v7
  Some minor fixup
v6
  Send the last two patches
v5
  A few modification at style, add the missing doc in the last 
  commit.
v4
  1. Adding the reset callback in struct phy_ops.
  2. Moving the reset into phy rockchip usb.
  3. Trying to call a reset when dwc2 wakeup in rk3288.
v3
 Rebased from previous commit.

Randy Li (4):
  phy: Add reset callback
  phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during
    wakeup
  usb: dwc2: assert phy reset when waking up in rk3288 platform
  ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

 .../devicetree/bindings/phy/rockchip-usb-phy.txt     |  3 +++
 arch/arm/boot/dts/rk3288.dtsi                        |  4 ++++
 drivers/phy/phy-rockchip-usb.c                       | 20 ++++++++++++++++++++
 drivers/usb/dwc2/core_intr.c                         | 12 ++++++++++++
 include/linux/phy/phy.h                              |  2 ++
 5 files changed, 41 insertions(+)

-- 
2.7.4

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[PATCH v7 1/4] phy: Add reset callback

[Randy Li]

The only use for this is for solving a hardware design problem in
usb of Rockchip RK3288.

Signed-off-by: Randy Li <ayaka@soulik.info>
---
 include/linux/phy/phy.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index f08b672..4d34607 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -36,6 +36,7 @@ enum phy_mode {
  * @power_on: powering on the phy
  * @power_off: powering off the phy
  * @set_mode: set the mode of the phy
+ * @reset: reseting the phy
  * @owner: the module owner containing the ops
  */
 struct phy_ops {
@@ -44,6 +45,7 @@ struct phy_ops {
 	int	(*power_on)(struct phy *phy);
 	int	(*power_off)(struct phy *phy);
 	int	(*set_mode)(struct phy *phy, enum phy_mode mode);
+	int	(*reset)(struct phy *phy);
 	struct module *owner;
 };
 
-- 
2.7.4

[PATCH v7 1/4] phy: Add reset callback

[Randy Li]

The only use for this is for solving a hardware design problem in
usb of Rockchip RK3288.

Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
---
 include/linux/phy/phy.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index f08b672..4d34607 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -36,6 +36,7 @@ enum phy_mode {
  * @power_on: powering on the phy
  * @power_off: powering off the phy
  * @set_mode: set the mode of the phy
+ * @reset: reseting the phy
  * @owner: the module owner containing the ops
  */
 struct phy_ops {
@@ -44,6 +45,7 @@ struct phy_ops {
 	int	(*power_on)(struct phy *phy);
 	int	(*power_off)(struct phy *phy);
 	int	(*set_mode)(struct phy *phy, enum phy_mode mode);
+	int	(*reset)(struct phy *phy);
 	struct module *owner;
 };
 
-- 
2.7.4

[PATCH v7 2/4] phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during wakeup

[Randy Li]

It is a hardware bug in RK3288, the only way to solve it is to
reset the phy.

Signed-off-by: Randy Li <ayaka@soulik.info>
---
 .../devicetree/bindings/phy/rockchip-usb-phy.txt     |  3 +++
 drivers/phy/phy-rockchip-usb.c                       | 20 ++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
index cc6be96..57dc388 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -27,6 +27,9 @@ Optional Properties:
 - clocks : phandle + clock specifier for the phy clocks
 - clock-names: string, clock name, must be "phyclk"
 - #clock-cells: for users of the phy-pll, should be 0
+- reset-names: Only allow the following entries:
+ - phy-reset
+- resets: Must contain an entry for each entry in reset-names.
 
 Example:
 
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
index 2a7381f..734987f 100644
--- a/drivers/phy/phy-rockchip-usb.c
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -29,6 +29,7 @@
 #include <linux/reset.h>
 #include <linux/regmap.h>
 #include <linux/mfd/syscon.h>
+#include <linux/delay.h>
 
 static int enable_usb_uart;
 
@@ -64,6 +65,7 @@ struct rockchip_usb_phy {
 	struct clk_hw	clk480m_hw;
 	struct phy	*phy;
 	bool		uart_enabled;
+	struct reset_control *reset;
 };
 
 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
@@ -144,9 +146,23 @@ static int rockchip_usb_phy_power_on(struct phy *_phy)
 	return clk_prepare_enable(phy->clk480m);
 }
 
+static int rockchip_usb_phy_reset(struct phy *_phy)
+{
+	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+
+	if (phy->reset) {
+		reset_control_assert(phy->reset);
+		udelay(10);
+		reset_control_deassert(phy->reset);
+	}
+
+	return 0;
+}
+
 static const struct phy_ops ops = {
 	.power_on	= rockchip_usb_phy_power_on,
 	.power_off	= rockchip_usb_phy_power_off,
+	.reset		= rockchip_usb_phy_reset,
 	.owner		= THIS_MODULE,
 };
 
@@ -185,6 +201,10 @@ static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
 		return -EINVAL;
 	}
 
+	rk_phy->reset = of_reset_control_get(child, "phy-reset");
+	if (IS_ERR(rk_phy->reset))
+		rk_phy->reset = NULL;
+
 	rk_phy->reg_offset = reg_offset;
 
 	rk_phy->clk = of_clk_get_by_name(child, "phyclk");
-- 
2.7.4

[PATCH v7 2/4] phy: rockchip-usb: use rockchip_usb_phy_reset to reset phy during wakeup

[Randy Li]

It is a hardware bug in RK3288, the only way to solve it is to
reset the phy.

Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
---
 .../devicetree/bindings/phy/rockchip-usb-phy.txt     |  3 +++
 drivers/phy/phy-rockchip-usb.c                       | 20 ++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
index cc6be96..57dc388 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -27,6 +27,9 @@ Optional Properties:
 - clocks : phandle + clock specifier for the phy clocks
 - clock-names: string, clock name, must be "phyclk"
 - #clock-cells: for users of the phy-pll, should be 0
+- reset-names: Only allow the following entries:
+ - phy-reset
+- resets: Must contain an entry for each entry in reset-names.
 
 Example:
 
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
index 2a7381f..734987f 100644
--- a/drivers/phy/phy-rockchip-usb.c
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -29,6 +29,7 @@
 #include <linux/reset.h>
 #include <linux/regmap.h>
 #include <linux/mfd/syscon.h>
+#include <linux/delay.h>
 
 static int enable_usb_uart;
 
@@ -64,6 +65,7 @@ struct rockchip_usb_phy {
 	struct clk_hw	clk480m_hw;
 	struct phy	*phy;
 	bool		uart_enabled;
+	struct reset_control *reset;
 };
 
 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
@@ -144,9 +146,23 @@ static int rockchip_usb_phy_power_on(struct phy *_phy)
 	return clk_prepare_enable(phy->clk480m);
 }
 
+static int rockchip_usb_phy_reset(struct phy *_phy)
+{
+	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+
+	if (phy->reset) {
+		reset_control_assert(phy->reset);
+		udelay(10);
+		reset_control_deassert(phy->reset);
+	}
+
+	return 0;
+}
+
 static const struct phy_ops ops = {
 	.power_on	= rockchip_usb_phy_power_on,
 	.power_off	= rockchip_usb_phy_power_off,
+	.reset		= rockchip_usb_phy_reset,
 	.owner		= THIS_MODULE,
 };
 
@@ -185,6 +201,10 @@ static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
 		return -EINVAL;
 	}
 
+	rk_phy->reset = of_reset_control_get(child, "phy-reset");
+	if (IS_ERR(rk_phy->reset))
+		rk_phy->reset = NULL;
+
 	rk_phy->reg_offset = reg_offset;
 
 	rk_phy->clk = of_clk_get_by_name(child, "phyclk");
-- 
2.7.4

[PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ayaka@soulik.info>
---
 drivers/usb/dwc2/core_intr.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..08485b7 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
 	int ret;
+	struct device_node *np = hsotg->dev->of_node;
 
 	/* Clear interrupt */
 	dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 			/* Restart the Phy Clock */
 			pcgcctl &= ~PCGCTL_STOPPCLK;
 			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+			/*
+			 * It is a quirk in Rockchip RK3288, causing by
+			 * a hardware bug. This will propagate out and
+			 * eventually we'll re-enumerate the device. 
+			 * Not great but the best we can do 
+			 */
+			if (of_device_is_compatible(np, "rockchip,rk3288-usb")
+					&& (NULL != hsotg->phy->ops->reset))
+				hsotg->phy->ops->reset(hsotg->phy);
+
 			mod_timer(&hsotg->wkp_timer,
 				  jiffies + msecs_to_jiffies(71));
 		} else {
-- 
2.7.4

[PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Randy Li]

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
---
 drivers/usb/dwc2/core_intr.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index d85c5c9..08485b7 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 {
 	int ret;
+	struct device_node *np = hsotg->dev->of_node;
 
 	/* Clear interrupt */
 	dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
@@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 			/* Restart the Phy Clock */
 			pcgcctl &= ~PCGCTL_STOPPCLK;
 			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+
+			/*
+			 * It is a quirk in Rockchip RK3288, causing by
+			 * a hardware bug. This will propagate out and
+			 * eventually we'll re-enumerate the device. 
+			 * Not great but the best we can do 
+			 */
+			if (of_device_is_compatible(np, "rockchip,rk3288-usb")
+					&& (NULL != hsotg->phy->ops->reset))
+				hsotg->phy->ops->reset(hsotg->phy);
+
 			mod_timer(&hsotg->wkp_timer,
 				  jiffies + msecs_to_jiffies(71));
 		} else {
-- 
2.7.4

[PATCH v7 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Randy Li <ayaka@soulik.info>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 17ec2e2..34de803 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -857,6 +857,8 @@
 				clocks = <&cru SCLK_OTGPHY0>;
 				clock-names = "phyclk";
 				#clock-cells = <0>;
+				resets = <&cru SRST_USBOTG_PHY>;
+				reset-names = "phy-reset";
 			};
 
 			usbphy1: usb-phy@334 {
@@ -873,6 +875,8 @@
 				clocks = <&cru SCLK_OTGPHY2>;
 				clock-names = "phyclk";
 				#clock-cells = <0>;
+				resets = <&cru SRST_USBHOST1_PHY>;
+				reset-names = "phy-reset";
 			};
 		};
 	};
-- 
2.7.4

[PATCH v7 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset

[Randy Li]

The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup.  We'll use the reset that's in the CRU to reset the
port when it's in a bad state.

Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata.  Only the host port gets the
quirk property, though.

Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
---
 arch/arm/boot/dts/rk3288.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 17ec2e2..34de803 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -857,6 +857,8 @@
 				clocks = <&cru SCLK_OTGPHY0>;
 				clock-names = "phyclk";
 				#clock-cells = <0>;
+				resets = <&cru SRST_USBOTG_PHY>;
+				reset-names = "phy-reset";
 			};
 
 			usbphy1: usb-phy@334 {
@@ -873,6 +875,8 @@
 				clocks = <&cru SCLK_OTGPHY2>;
 				clock-names = "phyclk";
 				#clock-cells = <0>;
+				resets = <&cru SRST_USBHOST1_PHY>;
+				reset-names = "phy-reset";
 			};
 		};
 	};
-- 
2.7.4

Re: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Sergei Shtylyov]

On 09/04/2016 12:55 AM, Randy Li wrote:

> On the rk3288 USB host-only port (the one that's not the OTG-enabled
> port) the PHY can get into a bad state when a wakeup is asserted (not
> just a wakeup from full system suspend but also a wakeup from
> autosuspend).
>
> We can get the PHY out of its bad state by asserting its "port reset",
> but unfortunately that seems to assert a reset onto the USB bus so it
> could confuse things if we don't actually deenumerate / reenumerate the
> device.
>
> We can also get the PHY out of its bad state by fully resetting it using
> the reset from the CRU (clock reset unit) in chip, which does a more full
> reset.  The CRU-based reset appears to actually cause devices on the bus
> to be removed and reinserted, which fixes the problem (albeit in a hacky
> way).
>
> It's unfortunate that we need to do a full re-enumeration of devices at
> wakeup time, but this is better than alternative of letting the bus get
> wedged.
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> ---
>  drivers/usb/dwc2/core_intr.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
> index d85c5c9..08485b7 100644
> --- a/drivers/usb/dwc2/core_intr.c
> +++ b/drivers/usb/dwc2/core_intr.c
[...]
> @@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>  			/* Restart the Phy Clock */
>  			pcgcctl &= ~PCGCTL_STOPPCLK;
>  			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
> +
> +			/*
> +			 * It is a quirk in Rockchip RK3288, causing by
> +			 * a hardware bug. This will propagate out and
> +			 * eventually we'll re-enumerate the device.
> +			 * Not great but the best we can do
> +			 */
> +			if (of_device_is_compatible(np, "rockchip,rk3288-usb")
> +					&& (NULL != hsotg->phy->ops->reset))

    Don't reverse the operands of !=, please.

[...]

MBR, Sergei

Re: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Sergei Shtylyov]

On 09/04/2016 12:55 AM, Randy Li wrote:

> On the rk3288 USB host-only port (the one that's not the OTG-enabled
> port) the PHY can get into a bad state when a wakeup is asserted (not
> just a wakeup from full system suspend but also a wakeup from
> autosuspend).
>
> We can get the PHY out of its bad state by asserting its "port reset",
> but unfortunately that seems to assert a reset onto the USB bus so it
> could confuse things if we don't actually deenumerate / reenumerate the
> device.
>
> We can also get the PHY out of its bad state by fully resetting it using
> the reset from the CRU (clock reset unit) in chip, which does a more full
> reset.  The CRU-based reset appears to actually cause devices on the bus
> to be removed and reinserted, which fixes the problem (albeit in a hacky
> way).
>
> It's unfortunate that we need to do a full re-enumeration of devices at
> wakeup time, but this is better than alternative of letting the bus get
> wedged.
>
> Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
> ---
>  drivers/usb/dwc2/core_intr.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
> index d85c5c9..08485b7 100644
> --- a/drivers/usb/dwc2/core_intr.c
> +++ b/drivers/usb/dwc2/core_intr.c
[...]
> @@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>  			/* Restart the Phy Clock */
>  			pcgcctl &= ~PCGCTL_STOPPCLK;
>  			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
> +
> +			/*
> +			 * It is a quirk in Rockchip RK3288, causing by
> +			 * a hardware bug. This will propagate out and
> +			 * eventually we'll re-enumerate the device.
> +			 * Not great but the best we can do
> +			 */
> +			if (of_device_is_compatible(np, "rockchip,rk3288-usb")
> +					&& (NULL != hsotg->phy->ops->reset))

    Don't reverse the operands of !=, please.

[...]

MBR, Sergei

RE: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[David Laight]

From: Randy Li
> Sent: 03 September 2016 22:55
...
> +			if (of_device_is_compatible(np, "rockchip,rk3288-usb")
> +					&& (NULL != hsotg->phy->ops->reset))
> +				hsotg->phy->ops->reset(hsotg->phy);
> +

Is this the only place ops->reset() is called?
Probably much better to check it first.

			if (hsotg->phy->ops->reset
					&& of_device_is_compatible(np, "rockchip,rk3288-usb")
				hsotg->phy->ops->reset(hsotg->phy);

	David

RE: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[David Laight]

From: Randy Li
> Sent: 03 September 2016 22:55
...
> +			if (of_device_is_compatible(np, "rockchip,rk3288-usb")
> +					&& (NULL != hsotg->phy->ops->reset))
> +				hsotg->phy->ops->reset(hsotg->phy);
> +

Is this the only place ops->reset() is called?
Probably much better to check it first.

			if (hsotg->phy->ops->reset
					&& of_device_is_compatible(np, "rockchip,rk3288-usb")
				hsotg->phy->ops->reset(hsotg->phy);

	David

Re: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Ayaka]

從我的 iPad 傳送

> David Laight <David.Laight@ACULAB.COM> 於 2016年9月5日 下午9:35 寫道：
> 
> From: Randy Li
>> Sent: 03 September 2016 22:55
> ...
>> +            if (of_device_is_compatible(np, "rockchip,rk3288-usb")
>> +                    && (NULL != hsotg->phy->ops->reset))
>> +                hsotg->phy->ops->reset(hsotg->phy);
>> +
> 
> Is this the only place ops->reset() is called?
Yes.
> Probably much better to check it first.
Sure.
> 
>            if (hsotg->phy->ops->reset
>                    && of_device_is_compatible(np, "rockchip,rk3288-usb")
>                hsotg->phy->ops->reset(hsotg->phy);
I see, if there is no the other review request for this version, I would submit a new version to fix this problem tonight.
> 
>    David

Re: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Ayaka]

從我的 iPad 傳送

> David Laight <David.Laight-ZS65k/vG3HxXrIkS9f7CXA@public.gmane.org> 於 2016年9月5日 下午9:35 寫道：
> 
> From: Randy Li
>> Sent: 03 September 2016 22:55
> ...
>> +            if (of_device_is_compatible(np, "rockchip,rk3288-usb")
>> +                    && (NULL != hsotg->phy->ops->reset))
>> +                hsotg->phy->ops->reset(hsotg->phy);
>> +
> 
> Is this the only place ops->reset() is called?
Yes.
> Probably much better to check it first.
Sure.
> 
>            if (hsotg->phy->ops->reset
>                    && of_device_is_compatible(np, "rockchip,rk3288-usb")
>                hsotg->phy->ops->reset(hsotg->phy);
I see, if there is no the other review request for this version, I would submit a new version to fix this problem tonight.
> 
>    David

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Re: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Kishon Vijay Abraham I]

Hi,

On Sunday 04 September 2016 03:25 AM, Randy Li wrote:
> On the rk3288 USB host-only port (the one that's not the OTG-enabled
> port) the PHY can get into a bad state when a wakeup is asserted (not
> just a wakeup from full system suspend but also a wakeup from
> autosuspend).
> 
> We can get the PHY out of its bad state by asserting its "port reset",
> but unfortunately that seems to assert a reset onto the USB bus so it
> could confuse things if we don't actually deenumerate / reenumerate the
> device.
> 
> We can also get the PHY out of its bad state by fully resetting it using
> the reset from the CRU (clock reset unit) in chip, which does a more full
> reset.  The CRU-based reset appears to actually cause devices on the bus
> to be removed and reinserted, which fixes the problem (albeit in a hacky
> way).
> 
> It's unfortunate that we need to do a full re-enumeration of devices at
> wakeup time, but this is better than alternative of letting the bus get
> wedged.
> 
> Signed-off-by: Randy Li <ayaka@soulik.info>
> ---
>  drivers/usb/dwc2/core_intr.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
> index d85c5c9..08485b7 100644
> --- a/drivers/usb/dwc2/core_intr.c
> +++ b/drivers/usb/dwc2/core_intr.c
> @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
>  static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>  {
>  	int ret;
> +	struct device_node *np = hsotg->dev->of_node;
>  
>  	/* Clear interrupt */
>  	dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
> @@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>  			/* Restart the Phy Clock */
>  			pcgcctl &= ~PCGCTL_STOPPCLK;
>  			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
> +
> +			/*
> +			 * It is a quirk in Rockchip RK3288, causing by
> +			 * a hardware bug. This will propagate out and
> +			 * eventually we'll re-enumerate the device. 
> +			 * Not great but the best we can do 
> +			 */
> +			if (of_device_is_compatible(np, "rockchip,rk3288-usb")
> +					&& (NULL != hsotg->phy->ops->reset))
> +				hsotg->phy->ops->reset(hsotg->phy);

never call the phy ops directly from the controller driver. It has to be
protected as well.

Thanks
Kishon

Re: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Kishon Vijay Abraham I]

Hi,

On Sunday 04 September 2016 03:25 AM, Randy Li wrote:
> On the rk3288 USB host-only port (the one that's not the OTG-enabled
> port) the PHY can get into a bad state when a wakeup is asserted (not
> just a wakeup from full system suspend but also a wakeup from
> autosuspend).
> 
> We can get the PHY out of its bad state by asserting its "port reset",
> but unfortunately that seems to assert a reset onto the USB bus so it
> could confuse things if we don't actually deenumerate / reenumerate the
> device.
> 
> We can also get the PHY out of its bad state by fully resetting it using
> the reset from the CRU (clock reset unit) in chip, which does a more full
> reset.  The CRU-based reset appears to actually cause devices on the bus
> to be removed and reinserted, which fixes the problem (albeit in a hacky
> way).
> 
> It's unfortunate that we need to do a full re-enumeration of devices at
> wakeup time, but this is better than alternative of letting the bus get
> wedged.
> 
> Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
> ---
>  drivers/usb/dwc2/core_intr.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
> index d85c5c9..08485b7 100644
> --- a/drivers/usb/dwc2/core_intr.c
> +++ b/drivers/usb/dwc2/core_intr.c
> @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
>  static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>  {
>  	int ret;
> +	struct device_node *np = hsotg->dev->of_node;
>  
>  	/* Clear interrupt */
>  	dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
> @@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>  			/* Restart the Phy Clock */
>  			pcgcctl &= ~PCGCTL_STOPPCLK;
>  			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
> +
> +			/*
> +			 * It is a quirk in Rockchip RK3288, causing by
> +			 * a hardware bug. This will propagate out and
> +			 * eventually we'll re-enumerate the device. 
> +			 * Not great but the best we can do 
> +			 */
> +			if (of_device_is_compatible(np, "rockchip,rk3288-usb")
> +					&& (NULL != hsotg->phy->ops->reset))
> +				hsotg->phy->ops->reset(hsotg->phy);

never call the phy ops directly from the controller driver. It has to be
protected as well.

Thanks
Kishon

Re: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[John Youn]

On 9/5/2016 10:15 PM, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Sunday 04 September 2016 03:25 AM, Randy Li wrote:
>> On the rk3288 USB host-only port (the one that's not the OTG-enabled
>> port) the PHY can get into a bad state when a wakeup is asserted (not
>> just a wakeup from full system suspend but also a wakeup from
>> autosuspend).
>>
>> We can get the PHY out of its bad state by asserting its "port reset",
>> but unfortunately that seems to assert a reset onto the USB bus so it
>> could confuse things if we don't actually deenumerate / reenumerate the
>> device.
>>
>> We can also get the PHY out of its bad state by fully resetting it using
>> the reset from the CRU (clock reset unit) in chip, which does a more full
>> reset.  The CRU-based reset appears to actually cause devices on the bus
>> to be removed and reinserted, which fixes the problem (albeit in a hacky
>> way).
>>
>> It's unfortunate that we need to do a full re-enumeration of devices at
>> wakeup time, but this is better than alternative of letting the bus get
>> wedged.
>>
>> Signed-off-by: Randy Li <ayaka@soulik.info>
>> ---
>>  drivers/usb/dwc2/core_intr.c | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
>> index d85c5c9..08485b7 100644
>> --- a/drivers/usb/dwc2/core_intr.c
>> +++ b/drivers/usb/dwc2/core_intr.c
>> @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
>>  static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>  {
>>  	int ret;
>> +	struct device_node *np = hsotg->dev->of_node;
>>  
>>  	/* Clear interrupt */
>>  	dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
>> @@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>  			/* Restart the Phy Clock */
>>  			pcgcctl &= ~PCGCTL_STOPPCLK;
>>  			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
>> +
>> +			/*
>> +			 * It is a quirk in Rockchip RK3288, causing by
>> +			 * a hardware bug. This will propagate out and
>> +			 * eventually we'll re-enumerate the device. 
>> +			 * Not great but the best we can do 
>> +			 */
>> +			if (of_device_is_compatible(np, "rockchip,rk3288-usb")
>> +					&& (NULL != hsotg->phy->ops->reset))
>> +				hsotg->phy->ops->reset(hsotg->phy);
> 
> never call the phy ops directly from the controller driver. It has to be
> protected as well.

It looks like we should be calling an API function instead, correct?

Similar to the wrappers for the other ops.

Regards,
John

Re: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[John Youn]

On 9/5/2016 10:15 PM, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Sunday 04 September 2016 03:25 AM, Randy Li wrote:
>> On the rk3288 USB host-only port (the one that's not the OTG-enabled
>> port) the PHY can get into a bad state when a wakeup is asserted (not
>> just a wakeup from full system suspend but also a wakeup from
>> autosuspend).
>>
>> We can get the PHY out of its bad state by asserting its "port reset",
>> but unfortunately that seems to assert a reset onto the USB bus so it
>> could confuse things if we don't actually deenumerate / reenumerate the
>> device.
>>
>> We can also get the PHY out of its bad state by fully resetting it using
>> the reset from the CRU (clock reset unit) in chip, which does a more full
>> reset.  The CRU-based reset appears to actually cause devices on the bus
>> to be removed and reinserted, which fixes the problem (albeit in a hacky
>> way).
>>
>> It's unfortunate that we need to do a full re-enumeration of devices at
>> wakeup time, but this is better than alternative of letting the bus get
>> wedged.
>>
>> Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
>> ---
>>  drivers/usb/dwc2/core_intr.c | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
>> index d85c5c9..08485b7 100644
>> --- a/drivers/usb/dwc2/core_intr.c
>> +++ b/drivers/usb/dwc2/core_intr.c
>> @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
>>  static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>  {
>>  	int ret;
>> +	struct device_node *np = hsotg->dev->of_node;
>>  
>>  	/* Clear interrupt */
>>  	dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
>> @@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>  			/* Restart the Phy Clock */
>>  			pcgcctl &= ~PCGCTL_STOPPCLK;
>>  			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
>> +
>> +			/*
>> +			 * It is a quirk in Rockchip RK3288, causing by
>> +			 * a hardware bug. This will propagate out and
>> +			 * eventually we'll re-enumerate the device. 
>> +			 * Not great but the best we can do 
>> +			 */
>> +			if (of_device_is_compatible(np, "rockchip,rk3288-usb")
>> +					&& (NULL != hsotg->phy->ops->reset))
>> +				hsotg->phy->ops->reset(hsotg->phy);
> 
> never call the phy ops directly from the controller driver. It has to be
> protected as well.

It looks like we should be calling an API function instead, correct?

Similar to the wrappers for the other ops.

Regards,
John

Re: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Ayaka]

從我的 iPad 傳送

> John Youn <John.Youn@synopsys.com> 於 2016年9月7日 上午2:54 寫道：
> 
>> On 9/5/2016 10:15 PM, Kishon Vijay Abraham I wrote:
>> Hi,
>> 
>>> On Sunday 04 September 2016 03:25 AM, Randy Li wrote:
>>> On the rk3288 USB host-only port (the one that's not the OTG-enabled
>>> port) the PHY can get into a bad state when a wakeup is asserted (not
>>> just a wakeup from full system suspend but also a wakeup from
>>> autosuspend).
>>> 
>>> We can get the PHY out of its bad state by asserting its "port reset",
>>> but unfortunately that seems to assert a reset onto the USB bus so it
>>> could confuse things if we don't actually deenumerate / reenumerate the
>>> device.
>>> 
>>> We can also get the PHY out of its bad state by fully resetting it using
>>> the reset from the CRU (clock reset unit) in chip, which does a more full
>>> reset.  The CRU-based reset appears to actually cause devices on the bus
>>> to be removed and reinserted, which fixes the problem (albeit in a hacky
>>> way).
>>> 
>>> It's unfortunate that we need to do a full re-enumeration of devices at
>>> wakeup time, but this is better than alternative of letting the bus get
>>> wedged.
>>> 
>>> Signed-off-by: Randy Li <ayaka@soulik.info>
>>> ---
>>> drivers/usb/dwc2/core_intr.c | 12 ++++++++++++
>>> 1 file changed, 12 insertions(+)
>>> 
>>> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
>>> index d85c5c9..08485b7 100644
>>> --- a/drivers/usb/dwc2/core_intr.c
>>> +++ b/drivers/usb/dwc2/core_intr.c
>>> @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
>>> static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>> {
>>>    int ret;
>>> +    struct device_node *np = hsotg->dev->of_node;
>>> 
>>>    /* Clear interrupt */
>>>    dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
>>> @@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>>            /* Restart the Phy Clock */
>>>            pcgcctl &= ~PCGCTL_STOPPCLK;
>>>            dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
>>> +
>>> +            /*
>>> +             * It is a quirk in Rockchip RK3288, causing by
>>> +             * a hardware bug. This will propagate out and
>>> +             * eventually we'll re-enumerate the device. 
>>> +             * Not great but the best we can do 
>>> +             */
>>> +            if (of_device_is_compatible(np, "rockchip,rk3288-usb")
>>> +                    && (NULL != hsotg->phy->ops->reset))
>>> +                hsotg->phy->ops->reset(hsotg->phy);
>> 
>> never call the phy ops directly from the controller driver. It has to be
>> protected as well.
> 
> It looks like we should be calling an API function instead, correct?
> 
Could you give me a example for the wrapper of phy ops?
> Similar to the wrappers for the other ops.
> 
> Regards,
> John

Re: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[Ayaka]

從我的 iPad 傳送

> John Youn <John.Youn@synopsys.com> 於 2016年9月7日 上午2:54 寫道：
> 
>> On 9/5/2016 10:15 PM, Kishon Vijay Abraham I wrote:
>> Hi,
>> 
>>> On Sunday 04 September 2016 03:25 AM, Randy Li wrote:
>>> On the rk3288 USB host-only port (the one that's not the OTG-enabled
>>> port) the PHY can get into a bad state when a wakeup is asserted (not
>>> just a wakeup from full system suspend but also a wakeup from
>>> autosuspend).
>>> 
>>> We can get the PHY out of its bad state by asserting its "port reset",
>>> but unfortunately that seems to assert a reset onto the USB bus so it
>>> could confuse things if we don't actually deenumerate / reenumerate the
>>> device.
>>> 
>>> We can also get the PHY out of its bad state by fully resetting it using
>>> the reset from the CRU (clock reset unit) in chip, which does a more full
>>> reset.  The CRU-based reset appears to actually cause devices on the bus
>>> to be removed and reinserted, which fixes the problem (albeit in a hacky
>>> way).
>>> 
>>> It's unfortunate that we need to do a full re-enumeration of devices at
>>> wakeup time, but this is better than alternative of letting the bus get
>>> wedged.
>>> 
>>> Signed-off-by: Randy Li <ayaka@soulik.info>
>>> ---
>>> drivers/usb/dwc2/core_intr.c | 12 ++++++++++++
>>> 1 file changed, 12 insertions(+)
>>> 
>>> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
>>> index d85c5c9..08485b7 100644
>>> --- a/drivers/usb/dwc2/core_intr.c
>>> +++ b/drivers/usb/dwc2/core_intr.c
>>> @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
>>> static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>> {
>>>    int ret;
>>> +    struct device_node *np = hsotg->dev->of_node;
>>> 
>>>    /* Clear interrupt */
>>>    dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
>>> @@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>>            /* Restart the Phy Clock */
>>>            pcgcctl &= ~PCGCTL_STOPPCLK;
>>>            dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
>>> +
>>> +            /*
>>> +             * It is a quirk in Rockchip RK3288, causing by
>>> +             * a hardware bug. This will propagate out and
>>> +             * eventually we'll re-enumerate the device. 
>>> +             * Not great but the best we can do 
>>> +             */
>>> +            if (of_device_is_compatible(np, "rockchip,rk3288-usb")
>>> +                    && (NULL != hsotg->phy->ops->reset))
>>> +                hsotg->phy->ops->reset(hsotg->phy);
>> 
>> never call the phy ops directly from the controller driver. It has to be
>> protected as well.
> 
> It looks like we should be calling an API function instead, correct?
> 
Could you give me a example for the wrapper of phy ops?
> Similar to the wrappers for the other ops.
> 
> Regards,
> John


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Re: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[John Youn]

On 9/6/2016 6:19 PM, Ayaka wrote:
> 
> 
> 從我的 iPad 傳送
> 
>> John Youn <John.Youn@synopsys.com> 於 2016年9月7日 上午2:54 寫道：
>>
>>> On 9/5/2016 10:15 PM, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>>> On Sunday 04 September 2016 03:25 AM, Randy Li wrote:
>>>> On the rk3288 USB host-only port (the one that's not the OTG-enabled
>>>> port) the PHY can get into a bad state when a wakeup is asserted (not
>>>> just a wakeup from full system suspend but also a wakeup from
>>>> autosuspend).
>>>>
>>>> We can get the PHY out of its bad state by asserting its "port reset",
>>>> but unfortunately that seems to assert a reset onto the USB bus so it
>>>> could confuse things if we don't actually deenumerate / reenumerate the
>>>> device.
>>>>
>>>> We can also get the PHY out of its bad state by fully resetting it using
>>>> the reset from the CRU (clock reset unit) in chip, which does a more full
>>>> reset.  The CRU-based reset appears to actually cause devices on the bus
>>>> to be removed and reinserted, which fixes the problem (albeit in a hacky
>>>> way).
>>>>
>>>> It's unfortunate that we need to do a full re-enumeration of devices at
>>>> wakeup time, but this is better than alternative of letting the bus get
>>>> wedged.
>>>>
>>>> Signed-off-by: Randy Li <ayaka@soulik.info>
>>>> ---
>>>> drivers/usb/dwc2/core_intr.c | 12 ++++++++++++
>>>> 1 file changed, 12 insertions(+)
>>>>
>>>> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
>>>> index d85c5c9..08485b7 100644
>>>> --- a/drivers/usb/dwc2/core_intr.c
>>>> +++ b/drivers/usb/dwc2/core_intr.c
>>>> @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
>>>> static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>>> {
>>>>    int ret;
>>>> +    struct device_node *np = hsotg->dev->of_node;
>>>>
>>>>    /* Clear interrupt */
>>>>    dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
>>>> @@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>>>            /* Restart the Phy Clock */
>>>>            pcgcctl &= ~PCGCTL_STOPPCLK;
>>>>            dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
>>>> +
>>>> +            /*
>>>> +             * It is a quirk in Rockchip RK3288, causing by
>>>> +             * a hardware bug. This will propagate out and
>>>> +             * eventually we'll re-enumerate the device. 
>>>> +             * Not great but the best we can do 
>>>> +             */
>>>> +            if (of_device_is_compatible(np, "rockchip,rk3288-usb")
>>>> +                    && (NULL != hsotg->phy->ops->reset))
>>>> +                hsotg->phy->ops->reset(hsotg->phy);
>>>
>>> never call the phy ops directly from the controller driver. It has to be
>>> protected as well.
>>
>> It looks like we should be calling an API function instead, correct?
>>
> Could you give me a example for the wrapper of phy ops?

Check these files:
* include/linux/phy/phy.h
* drivers/phy/phy-core.c

Search for "phy_set_mode".

I'm thinking there should be a "phy_reset" API function which calls
the phy->ops->reset in a similar manner. With the same runtime checks
and stub function if CONFIG_GENERIC_PHY is not enabled.

Regards,
John

Re: [PATCH v7 3/4] usb: dwc2: assert phy reset when waking up in rk3288 platform

[John Youn]

On 9/6/2016 6:19 PM, Ayaka wrote:
> 
> 
> 從我的 iPad 傳送
> 
>> John Youn <John.Youn-HKixBCOQz3hWk0Htik3J/w@public.gmane.org> 於 2016年9月7日 上午2:54 寫道：
>>
>>> On 9/5/2016 10:15 PM, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>>> On Sunday 04 September 2016 03:25 AM, Randy Li wrote:
>>>> On the rk3288 USB host-only port (the one that's not the OTG-enabled
>>>> port) the PHY can get into a bad state when a wakeup is asserted (not
>>>> just a wakeup from full system suspend but also a wakeup from
>>>> autosuspend).
>>>>
>>>> We can get the PHY out of its bad state by asserting its "port reset",
>>>> but unfortunately that seems to assert a reset onto the USB bus so it
>>>> could confuse things if we don't actually deenumerate / reenumerate the
>>>> device.
>>>>
>>>> We can also get the PHY out of its bad state by fully resetting it using
>>>> the reset from the CRU (clock reset unit) in chip, which does a more full
>>>> reset.  The CRU-based reset appears to actually cause devices on the bus
>>>> to be removed and reinserted, which fixes the problem (albeit in a hacky
>>>> way).
>>>>
>>>> It's unfortunate that we need to do a full re-enumeration of devices at
>>>> wakeup time, but this is better than alternative of letting the bus get
>>>> wedged.
>>>>
>>>> Signed-off-by: Randy Li <ayaka-xPW3/0Ywev/iB9QmIjCX8w@public.gmane.org>
>>>> ---
>>>> drivers/usb/dwc2/core_intr.c | 12 ++++++++++++
>>>> 1 file changed, 12 insertions(+)
>>>>
>>>> diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
>>>> index d85c5c9..08485b7 100644
>>>> --- a/drivers/usb/dwc2/core_intr.c
>>>> +++ b/drivers/usb/dwc2/core_intr.c
>>>> @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
>>>> static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>>> {
>>>>    int ret;
>>>> +    struct device_node *np = hsotg->dev->of_node;
>>>>
>>>>    /* Clear interrupt */
>>>>    dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
>>>> @@ -379,6 +380,17 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
>>>>            /* Restart the Phy Clock */
>>>>            pcgcctl &= ~PCGCTL_STOPPCLK;
>>>>            dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
>>>> +
>>>> +            /*
>>>> +             * It is a quirk in Rockchip RK3288, causing by
>>>> +             * a hardware bug. This will propagate out and
>>>> +             * eventually we'll re-enumerate the device. 
>>>> +             * Not great but the best we can do 
>>>> +             */
>>>> +            if (of_device_is_compatible(np, "rockchip,rk3288-usb")
>>>> +                    && (NULL != hsotg->phy->ops->reset))
>>>> +                hsotg->phy->ops->reset(hsotg->phy);
>>>
>>> never call the phy ops directly from the controller driver. It has to be
>>> protected as well.
>>
>> It looks like we should be calling an API function instead, correct?
>>
> Could you give me a example for the wrapper of phy ops?

Check these files:
* include/linux/phy/phy.h
* drivers/phy/phy-core.c

Search for "phy_set_mode".

I'm thinking there should be a "phy_reset" API function which calls
the phy->ops->reset in a similar manner. With the same runtime checks
and stub function if CONFIG_GENERIC_PHY is not enabled.

Regards,
John
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