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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Tue, 06 Sep 2016 13:05:07 +1000
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Subject: Re: [Qemu-devel] [PATCH RFC 4/4] target-ppc: flush tlb from all the
 cpu
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To: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>, Alex =?ISO-8859-1?Q?Benn=E9e?= <alex.bennee@linaro.org>
Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, qemu-devel@nongnu.org

On Tue, 2016-09-06 at 07:25 +0530, Nikunj A Dadhania wrote:
> > Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
>=20
> >=20
> > On Sun, 2016-09-04 at 18:00 +0100, Alex Benn=C3=A9e wrote:
> >=20
> > >=20
> > > When is the synchronisation point? On ARM we end the basic block on
> > > system instructions that mess with the cache. As a result the flush
> > > is done as soon as we exit the run loop on the next instruction.
> >=20
> > Talking o this... Nikunj, I notice, all our TLB flushing is only ever
> > done on the "current" CPU. I mean today, without MT-TCG. That looks
> > broken already isn't it ?
>=20
> Without MT-TCG, there was only one cpu, so I think we never hit that
> issue.

No there isn't. You can start qemu with --smp 4 and have 4 CPUs. It
will alternate between them, but they *will* have differrent TLBs.