From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47960) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh7E0-0000lD-M2 for qemu-devel@nongnu.org; Mon, 05 Sep 2016 23:39:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bh7Dy-000719-IB for qemu-devel@nongnu.org; Mon, 05 Sep 2016 23:39:03 -0400 From: David Gibson Date: Tue, 6 Sep 2016 13:40:01 +1000 Message-Id: <1473133253-17598-15-git-send-email-david@gibson.dropbear.id.au> In-Reply-To: <1473133253-17598-1-git-send-email-david@gibson.dropbear.id.au> References: <1473133253-17598-1-git-send-email-david@gibson.dropbear.id.au> Subject: [Qemu-devel] [PULL 14/66] target-ppc: add maddhd and maddhdu instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linearo.org Cc: agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Nikunj A Dadhania , David Gibson From: Nikunj A Dadhania maddhd: Multiply-Add High Doubleword maddhdu: Multiply-Add High Doubleword Unsigned Above two instruction are dual form and differ by 1 bit (31st bit) Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the higher dword in the target register(RT). Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target-ppc/translate.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 488a105..0b21ea2 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7749,6 +7749,29 @@ static void gen_maddld(DisasContext *ctx) tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); tcg_temp_free_i64(t1); } + +/* maddhd maddhdu */ +static void gen_maddhd_maddhdu(DisasContext *ctx) +{ + TCGv_i64 lo = tcg_temp_new_i64(); + TCGv_i64 hi = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + + if (Rc(ctx->opcode)) { + tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], + cpu_gpr[rB(ctx->opcode)]); + tcg_gen_movi_i64(t1, 0); + } else { + tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], + cpu_gpr[rB(ctx->opcode)]); + tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); + } + tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, + cpu_gpr[rC(ctx->opcode)], t1); + tcg_temp_free_i64(lo); + tcg_temp_free_i64(hi); + tcg_temp_free_i64(t1); +} #endif /* defined(TARGET_PPC64) */ GEN_VXFORM_NOA(vclzb, 1, 28) @@ -10367,6 +10390,8 @@ GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), #if defined(TARGET_PPC64) +GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, + PPC2_ISA300), GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), #endif GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), -- 2.7.4