From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48385) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bh7EC-0000y6-LH for qemu-devel@nongnu.org; Mon, 05 Sep 2016 23:39:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bh7E5-00079J-1B for qemu-devel@nongnu.org; Mon, 05 Sep 2016 23:39:15 -0400 From: David Gibson Date: Tue, 6 Sep 2016 13:40:33 +1000 Message-Id: <1473133253-17598-47-git-send-email-david@gibson.dropbear.id.au> In-Reply-To: <1473133253-17598-1-git-send-email-david@gibson.dropbear.id.au> References: <1473133253-17598-1-git-send-email-david@gibson.dropbear.id.au> Subject: [Qemu-devel] [PULL 46/66] target-ppc: implement branch-less divw[o][.] List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linearo.org Cc: agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Nikunj A Dadhania , David Gibson From: Nikunj A Dadhania While implementing modulo instructions figured out that the implementation uses many branches. Change the logic to achieve the branch-less code. Undefined value is set to dividend in case of invalid input. Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target-ppc/translate.c | 48 +++++++++++++++++++++++------------------------- 1 file changed, 23 insertions(+), 25 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 379d3d4..f69836d 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1097,41 +1097,39 @@ static void gen_addpcis(DisasContext *ctx) static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, int sign, int compute_ov) { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGv_i32 t0 = tcg_temp_local_new_i32(); - TCGv_i32 t1 = tcg_temp_local_new_i32(); + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_i32 t3 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t0, arg1); tcg_gen_trunc_tl_i32(t1, arg2); - tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); - if (sign) { - TCGLabel *l3 = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); - tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); - gen_set_label(l3); - tcg_gen_div_i32(t0, t0, t1); - } else { - tcg_gen_divu_i32(t0, t0, t1); - } - if (compute_ov) { - tcg_gen_movi_tl(cpu_ov, 0); - } - tcg_gen_br(l2); - gen_set_label(l1); if (sign) { - tcg_gen_sari_i32(t0, t0, 31); + tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); + tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); + tcg_gen_and_i32(t2, t2, t3); + tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); + tcg_gen_or_i32(t2, t2, t3); + tcg_gen_movi_i32(t3, 0); + tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_div_i32(t3, t0, t1); + tcg_gen_extu_i32_tl(ret, t3); } else { - tcg_gen_movi_i32(t0, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); + tcg_gen_movi_i32(t3, 0); + tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_divu_i32(t3, t0, t1); + tcg_gen_extu_i32_tl(ret, t3); } if (compute_ov) { - tcg_gen_movi_tl(cpu_ov, 1); - tcg_gen_movi_tl(cpu_so, 1); + tcg_gen_extu_i32_tl(cpu_ov, t2); + tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); } - gen_set_label(l2); - tcg_gen_extu_i32_tl(ret, t0); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx, ret); } -- 2.7.4