From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chin Liang See <clsee@altera.com>
Date: Tue, 6 Sep 2016 14:19:15 +0800
Subject: [U-Boot] [PATCH 06/11] arm: socfpga: misc: Segregate the misc.c
 for Stratix 10
In-Reply-To: <8589bb57-d3a5-9edf-1f95-78dc9d7485a5@denx.de>
References: <1471878163-3598-1-git-send-email-clsee@altera.com>
 <1471878163-3598-7-git-send-email-clsee@altera.com>
 <8589bb57-d3a5-9edf-1f95-78dc9d7485a5@denx.de>
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On Mon, 2016-09-05 at 18:01 +0200, Marek Vasut wrote:
> On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > Segregate the misc.c to support both GEN5 SoC and Stratix 10 SoC.
> > 
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Ley Foon Tan <lftan@altera.com>
> > ---
> >  arch/arm/mach-socfpga/misc.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach
> > -socfpga/misc.c
> > index 5cbd8a4..295121f 100644
> > --- a/arch/arm/mach-socfpga/misc.c
> > +++ b/arch/arm/mach-socfpga/misc.c
> > @@ -24,6 +24,8 @@
> >  
> >  DECLARE_GLOBAL_DATA_PTR;
> >  
> > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > +
> >  static struct pl310_regs *const pl310 =
> >  	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> >  static struct socfpga_system_manager *sysmgr_regs =
> > @@ -34,6 +36,7 @@ static struct nic301_registers *nic301_regs =
> >  	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> >  static struct scu_registers *scu_regs =
> >  	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> > +#endif
> >  
> >  int dram_init(void)
> >  {
> > @@ -41,6 +44,7 @@ int dram_init(void)
> >  	return 0;
> >  }
> >  
> > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> >  void enable_caches(void)
> >  {
> >  #ifndef CONFIG_SYS_ICACHE_OFF
> > @@ -246,6 +250,7 @@ static int socfpga_fpga_id(const bool print_id)
> >  		       socfpga_fpga_model[i].name, version);
> >  	return i;
> >  }
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> >  
> >  /*
> >   * Print CPU information
> > @@ -253,14 +258,20 @@ static int socfpga_fpga_id(const bool
> > print_id)
> >  #if defined(CONFIG_DISPLAY_CPUINFO)
> >  int print_cpuinfo(void)
> >  {
> > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> >  	const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
> >  	puts("CPU:   Altera SoCFPGA Platform\n");
> >  	socfpga_fpga_id(1);
> >  	printf("BOOT:  %s\n", bsel_str[bsel].name);
> > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > +	puts("CPU:   Altera SoCFPGA Platform\n");
> > +	puts("FPGA:  Altera Stratix 10\n");
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> 
> Can't you decode the boot mode and FPGA type instead ?

That is a good question. This is now not available in SOC Virtual
Platform. But will definitely enhance this in later stage with hardware
available.

Thanks
Chin Liang

> 
> >  	return 0;
> >  }
> >  #endif
> >  
> > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> >  #ifdef CONFIG_ARCH_MISC_INIT
> >  int arch_misc_init(void)
> >  {
> > @@ -469,3 +480,4 @@ U_BOOT_CMD(
> >  	"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS
> > -to-FPGA bridges\n"
> >  	""
> >  );
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > 
> 
>