From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chin Liang See Date: Tue, 6 Sep 2016 18:03:23 +0800 Subject: [U-Boot] [PATCH v2 05/11] arm: socfpga: fpgamgr: Disable FPGA Manager for Stratix 10 In-Reply-To: <1473156209-5734-1-git-send-email-clsee@altera.com> References: <1473156209-5734-1-git-send-email-clsee@altera.com> Message-ID: <1473156209-5734-6-git-send-email-clsee@altera.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Disable the FPGA Manager for Stratix 10 SoC as we are not using this for SOCVP Signed-off-by: Chin Liang See Cc: Marek Vasut Cc: Dinh Nguyen Cc: Ley Foon Tan --- Changes for v2 - Change in Makefile instead of fpga_manger.c --- arch/arm/mach-socfpga/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 809cd47..a8ea277 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -8,12 +8,13 @@ # obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ - fpga_manager.o board.o + board.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o # QTS-generated config file wrappers -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ + fpga_manager.o obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ wrap_sdram_config.o CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) -- 2.2.2