[U-Boot] [PATCH] fsl-ifc-nand : Corrected the programming of chip select

[U-Boot] [PATCH] fsl-ifc-nand : Corrected the programming of chip select

[Matt Weber]

Corrected the chip selection in IFC_NAND_CSEL register. Due to this
issue in multi-chip nand use-case, IFC was always pointing to the last
probed chip even though the user select another device through "nand
device" command.

Signed-off-by: Ronak Desai <ronak.desai@rockwellcollins.com>
Signed-off-by: Matthew Weber <matthew.weber@rockwellcollins.com>
---
 drivers/mtd/nand/fsl_ifc_nand.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 7001cbd..2ce4a7d 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -296,7 +296,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
 	int i;
 
 	/* set the chip select for NAND Transaction */
-	ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+	ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
 
 	/* start read/write seq */
 	ifc_out32(&ifc->ifc_nand.nandseq_strt,
-- 
1.9.1

[U-Boot] [PATCH] fsl-ifc-nand : Corrected the programming of chip select

[Scott Wood]

On 09/06/2016 08:44 AM, Matt Weber wrote:
> Corrected the chip selection in IFC_NAND_CSEL register. Due to this
> issue in multi-chip nand use-case, IFC was always pointing to the last
> probed chip even though the user select another device through "nand
> device" command.
> 
> Signed-off-by: Ronak Desai <ronak.desai@rockwellcollins.com>
> Signed-off-by: Matthew Weber <matthew.weber@rockwellcollins.com>
> ---
>  drivers/mtd/nand/fsl_ifc_nand.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
> index 7001cbd..2ce4a7d 100644
> --- a/drivers/mtd/nand/fsl_ifc_nand.c
> +++ b/drivers/mtd/nand/fsl_ifc_nand.c
> @@ -296,7 +296,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
>  	int i;
>  
>  	/* set the chip select for NAND Transaction */
> -	ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
> +	ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
>  
>  	/* start read/write seq */
>  	ifc_out32(&ifc->ifc_nand.nandseq_strt,

Ouch.  fsl_ifc_sram_init() should also be updated and cs_nand removed.

-Scott

[U-Boot] [PATCH] fsl-ifc-nand : Corrected the programming of chip select

[Ronak Desai]

We don't need to update fsl_ifc_sram_init() as fsl_ifc_sram_init is called
from the fsl_ifc_chip_init which configures the ifc_ctrl->cs_nand
with correct value based on the chip-select under initialization.

Best Regards,
Ronak Desai


On Tue, Sep 6, 2016 at 12:01 PM, Scott Wood <scott.wood@nxp.com> wrote:

> On 09/06/2016 08:44 AM, Matt Weber wrote:
> > Corrected the chip selection in IFC_NAND_CSEL register. Due to this
> > issue in multi-chip nand use-case, IFC was always pointing to the last
> > probed chip even though the user select another device through "nand
> > device" command.
> >
> > Signed-off-by: Ronak Desai <ronak.desai@rockwellcollins.com>
> > Signed-off-by: Matthew Weber <matthew.weber@rockwellcollins.com>
> > ---
> >  drivers/mtd/nand/fsl_ifc_nand.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_
> nand.c
> > index 7001cbd..2ce4a7d 100644
> > --- a/drivers/mtd/nand/fsl_ifc_nand.c
> > +++ b/drivers/mtd/nand/fsl_ifc_nand.c
> > @@ -296,7 +296,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
> >       int i;
> >
> >       /* set the chip select for NAND Transaction */
> > -     ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
> > +     ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank <<
> IFC_NAND_CSEL_SHIFT);
> >
> >       /* start read/write seq */
> >       ifc_out32(&ifc->ifc_nand.nandseq_strt,
>
> Ouch.  fsl_ifc_sram_init() should also be updated and cs_nand removed.
>
> -Scott
>
>

[U-Boot] [PATCH] fsl-ifc-nand : Corrected the programming of chip select

[Scott Wood]

On 09/06/2016 02:31 PM, Ronak Desai wrote:
> We don't need to update fsl_ifc_sram_init() as fsl_ifc_sram_init is
> called from the fsl_ifc_chip_init which configures the ifc_ctrl->cs_nand
> with correct value based on the chip-select under initialization. 
> 
> Best Regards,
> Ronak Desai

We don't *need* to but we should.  Chipselect is a property of the chip,
not the controller, so it doesn't belong in the controller struct
(unless it's going to be updated per-transaction like page, column, etc.
but we already have priv->bank so let's just use it).

-Scott

[U-Boot] [PATCH] fsl-ifc-nand : Corrected the programming of chip select

[Ronak Desai]

Corrected the chip selection in IFC_NAND_CSEL register. Due to this
issue in multi-chip nand use-case, IFC was always pointing to the last
probed chip even though user select another device through "nand device
<dev>" command.

Also, updated the driver to remove usage of ifc_ctrl->cs_nand as it's
the property of chip not the controller.

Signed-off-by: Ronak Desai <ronak.desai@rockwellcollins.com>
---
 drivers/mtd/nand/fsl_ifc_nand.c |   15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 495e3aa..2d0ca54 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -48,7 +48,6 @@ struct fsl_ifc_ctrl {
	/* device info */
	struct fsl_ifc regs;
	void __iomem *addr;      /* Address of assigned IFC buffer        */
-	unsigned int cs_nand;    /* On which chipsel NAND is connected	  */
	unsigned int page;       /* Last page written to / read from      */
	unsigned int read_bytes; /* Number of bytes read during command   */
	unsigned int column;     /* Saved column from SEQIN               */
@@ -296,7 +295,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
	int i;

	/* set the chip select for NAND Transaction */
-	ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+	ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);

	/* start read/write seq */
	ifc_out32(&ifc->ifc_nand.nandseq_strt,
@@ -821,7 +820,7 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 {
 }

-static int fsl_ifc_sram_init(uint32_t ver)
+static int fsl_ifc_sram_init(uint32_t ver, struct fsl_ifc_mtd *priv)
 {
	struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
	uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
@@ -846,7 +845,7 @@ static int fsl_ifc_sram_init(uint32_t ver)
		return 1;
	}

-	cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
+	cs = priv->bank;

	/* Save CSOR and CSOR_ext */
	csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
@@ -873,7 +872,7 @@ static int fsl_ifc_sram_init(uint32_t ver)
	ifc_out32(&ifc->ifc_nand.col0, 0x0);

	/* set the chip select for NAND Transaction */
-	ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+	ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);

	/* start read seq */
	ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
@@ -934,10 +933,8 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
		csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);

		if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
-		    (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
-			ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
+		    (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr))
			break;
-		}
	}

	if (priv->bank >= MAX_BANKS) {
@@ -1052,7 +1049,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)

	ver = ifc_in32(&gregs->ifc_rev);
	if (ver >= FSL_IFC_V1_1_0)
-		ret = fsl_ifc_sram_init(ver);
+		ret = fsl_ifc_sram_init(ver, priv);
	if (ret)
		return ret;

--
1.7.9.5