From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752854AbcIGFhl (ORCPT ); Wed, 7 Sep 2016 01:37:41 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:52866 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751254AbcIGFhi (ORCPT ); Wed, 7 Sep 2016 01:37:38 -0400 Message-ID: <1473226653.11736.33.camel@mtksdaap41> Subject: Re: [PATCH v7 9/9] drm/mediatek: add support for Mediatek SoC MT2701 From: CK Hu To: YT Shen CC: , Philipp Zabel , David Airlie , Matthias Brugger , Daniel Kurtz , Mao Huang , Bibby Hsieh , "Daniel Vetter" , Thierry Reding , Jie Qiu , Maxime Ripard , Chris Wilson , shaoming chen , Jitao Shi , Boris Brezillon , Dan Carpenter , , , , , Sascha Hauer , , Date: Wed, 7 Sep 2016 13:37:33 +0800 In-Reply-To: <1472815484-43821-10-git-send-email-yt.shen@mediatek.com> References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> <1472815484-43821-10-git-send-email-yt.shen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, YT: On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote: > This patch add support for the Mediatek MT2701 DISP subsystem. > There is only one OVL engine in MT2701. > > Signed-off-by: YT Shen [snip...] > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 4b4e449..465819b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -112,6 +112,7 @@ struct mtk_ddp_comp_match { > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, NULL }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_PWM, 0, NULL }, I think BLS is different than PWM, so this statement should be [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }; > [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, Regards, CK From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [PATCH v7 9/9] drm/mediatek: add support for Mediatek SoC MT2701 Date: Wed, 7 Sep 2016 13:37:33 +0800 Message-ID: <1473226653.11736.33.camel@mtksdaap41> References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> <1472815484-43821-10-git-send-email-yt.shen@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1472815484-43821-10-git-send-email-yt.shen@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: YT Shen Cc: Daniel Vetter , Jie Qiu , Mao Huang , yingjoe.chen@mediatek.com, Dan Carpenter , Jitao Shi , Sascha Hauer , linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, Matthias Brugger , shaoming chen , linux-arm-kernel@lists.infradead.org, srv_heupstream@mediatek.com, emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Maxime Ripard List-Id: linux-mediatek@lists.infradead.org SGksIFlUOgoKT24gRnJpLCAyMDE2LTA5LTAyIGF0IDE5OjI0ICswODAwLCBZVCBTaGVuIHdyb3Rl Ogo+IFRoaXMgcGF0Y2ggYWRkIHN1cHBvcnQgZm9yIHRoZSBNZWRpYXRlayBNVDI3MDEgRElTUCBz dWJzeXN0ZW0uCj4gVGhlcmUgaXMgb25seSBvbmUgT1ZMIGVuZ2luZSBpbiBNVDI3MDEuCj4gCj4g U2lnbmVkLW9mZi1ieTogWVQgU2hlbiA8eXQuc2hlbkBtZWRpYXRlay5jb20+Cgpbc25pcC4uLl0K Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21w LmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jCj4gaW5kZXgg NGI0ZTQ0OS4uNDY1ODE5YiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsv bXRrX2RybV9kZHBfY29tcC5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19k cm1fZGRwX2NvbXAuYwo+IEBAIC0xMTIsNiArMTEyLDcgQEAgc3RydWN0IG10a19kZHBfY29tcF9t YXRjaCB7Cj4gIAo+ICBzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9tYXRjaCBtdGtf ZGRwX21hdGNoZXNbRERQX0NPTVBPTkVOVF9JRF9NQVhdID0gewo+ICAJW0REUF9DT01QT05FTlRf QUFMXQk9IHsgTVRLX0RJU1BfQUFMLAkwLCBOVUxMIH0sCj4gKwlbRERQX0NPTVBPTkVOVF9CTFNd CT0geyBNVEtfRElTUF9QV00sCTAsIE5VTEwgfSwKCkkgdGhpbmsgQkxTIGlzIGRpZmZlcmVudCB0 aGFuIFBXTSwgc28gdGhpcyBzdGF0ZW1lbnQgc2hvdWxkIGJlCgpbRERQX0NPTVBPTkVOVF9CTFNd ID0geyBNVEtfRElTUF9CTFMsIDAsIE5VTEwgfTsKCgo+ICAJW0REUF9DT01QT05FTlRfQ09MT1Iw XQk9IHsgTVRLX0RJU1BfQ09MT1IsCTAsICZkZHBfY29sb3IgfSwKPiAgCVtERFBfQ09NUE9ORU5U X0NPTE9SMV0JPSB7IE1US19ESVNQX0NPTE9SLAkxLCAmZGRwX2NvbG9yIH0sCj4gIAlbRERQX0NP TVBPTkVOVF9EUEkwXQk9IHsgTVRLX0RQSSwJCTAsIE5VTEwgfSwKClJlZ2FyZHMsCkNLCgoKX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1h aWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMu ZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: ck.hu@mediatek.com (CK Hu) Date: Wed, 7 Sep 2016 13:37:33 +0800 Subject: [PATCH v7 9/9] drm/mediatek: add support for Mediatek SoC MT2701 In-Reply-To: <1472815484-43821-10-git-send-email-yt.shen@mediatek.com> References: <1472815484-43821-1-git-send-email-yt.shen@mediatek.com> <1472815484-43821-10-git-send-email-yt.shen@mediatek.com> Message-ID: <1473226653.11736.33.camel@mtksdaap41> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, YT: On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote: > This patch add support for the Mediatek MT2701 DISP subsystem. > There is only one OVL engine in MT2701. > > Signed-off-by: YT Shen [snip...] > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 4b4e449..465819b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -112,6 +112,7 @@ struct mtk_ddp_comp_match { > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, NULL }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_PWM, 0, NULL }, I think BLS is different than PWM, so this statement should be [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }; > [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, Regards, CK