From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gong Qianyu Date: Wed, 7 Sep 2016 17:56:11 +0800 Subject: [U-Boot] [Patch v6 6/9] armv8: ls1046a: Enable DDR erratum for ls1046a In-Reply-To: <1473242174-5807-1-git-send-email-Qianyu.Gong@nxp.com> References: <1473242174-5807-1-git-send-email-Qianyu.Gong@nxp.com> Message-ID: <1473242174-5807-7-git-send-email-Qianyu.Gong@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Shengzhou Liu Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803, ERRATUM_A009942, ERRATUM_A010165 Signed-off-by: Shengzhou Liu Signed-off-by: Gong Qianyu --- v3-v6: - No change. v2: - Add ERRATUM_A008511. arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 430c85b..329f08f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -236,6 +236,12 @@ #define GICC_BASE 0x01420000 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +#define CONFIG_SYS_FSL_ERRATUM_A008511 +#define CONFIG_SYS_FSL_ERRATUM_A009801 +#define CONFIG_SYS_FSL_ERRATUM_A009803 +#define CONFIG_SYS_FSL_ERRATUM_A009942 +#define CONFIG_SYS_FSL_ERRATUM_A010165 #else #error SoC not defined #endif -- 2.1.0.27.g96db324