From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gong Qianyu Date: Wed, 7 Sep 2016 17:56:12 +0800 Subject: [U-Boot] [Patch v6 7/9] armv8: ls1046a: disable SATA ECC in DCSR In-Reply-To: <1473242174-5807-1-git-send-email-Qianyu.Gong@nxp.com> References: <1473242174-5807-1-git-send-email-Qianyu.Gong@nxp.com> Message-ID: <1473242174-5807-8-git-send-email-Qianyu.Gong@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Shaohui Xie This is a workaround to fix SATA CRC error. Once the root cause is found the ECC disabling will be removed. Signed-off-by: Shaohui Xie Signed-off-by: Gong Qianyu --- v3-v6: - No change. v2: - Use values directly instead of macros. - Revise commit message. arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index f62b78d..a60c928 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -222,6 +222,10 @@ int sata_init(void) { struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; +#ifdef CONFIG_LS1046A + /* Disable SATA ECC */ + out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); +#endif out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); -- 2.1.0.27.g96db324