From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33367) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bha5c-0002cA-Ny for qemu-devel@nongnu.org; Wed, 07 Sep 2016 06:28:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bha5Y-0004ca-IS for qemu-devel@nongnu.org; Wed, 07 Sep 2016 06:28:20 -0400 From: David Gibson Date: Wed, 7 Sep 2016 20:28:51 +1000 Message-Id: <1473244183-31510-13-git-send-email-david@gibson.dropbear.id.au> In-Reply-To: <1473244183-31510-1-git-send-email-david@gibson.dropbear.id.au> References: <1473244183-31510-1-git-send-email-david@gibson.dropbear.id.au> Subject: [Qemu-devel] [PULL 12/64] target-ppc: add setb instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org Cc: agraf@suse.de, thuth@redhat.com, lvivier@redhat.com, benh@kernel.crashing.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Vivek Andrew Sha , Nikunj A Dadhania , David Gibson From: Vivek Andrew Sha The CR number is provided in the opcode as - BFA (11:13) Returns: -1 if bit 0 of CR field is set 1 if bit 1 of CR field is set 0 otherwise. Signed-off-by: Vivek Andrew Sha [ reworded commit, used 32bit ops as crf is 32bits ] Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target-ppc/translate.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index dd2ce58..1384fb7 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -4867,6 +4867,27 @@ static void gen_mtspr(DisasContext *ctx) } } +#if defined(TARGET_PPC64) +/* setb */ +static void gen_setb(DisasContext *ctx) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i32 t8 = tcg_temp_new_i32(); + TCGv_i32 tm1 = tcg_temp_new_i32(); + int crf = crfS(ctx->opcode); + + tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); + tcg_gen_movi_i32(t8, 8); + tcg_gen_movi_i32(tm1, -1); + tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); + tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); + + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t8); + tcg_temp_free_i32(tm1); +} +#endif + /*** Cache management ***/ /* dcbf */ @@ -10185,6 +10206,7 @@ GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), #if defined(TARGET_PPC64) GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), +GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), #endif GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), -- 2.7.4