From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33351) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bha5c-0002bY-Ny for qemu-devel@nongnu.org; Wed, 07 Sep 2016 06:28:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bha5X-0004bd-Ow for qemu-devel@nongnu.org; Wed, 07 Sep 2016 06:28:20 -0400 From: David Gibson Date: Wed, 7 Sep 2016 20:28:52 +1000 Message-Id: <1473244183-31510-14-git-send-email-david@gibson.dropbear.id.au> In-Reply-To: <1473244183-31510-1-git-send-email-david@gibson.dropbear.id.au> References: <1473244183-31510-1-git-send-email-david@gibson.dropbear.id.au> Subject: [Qemu-devel] [PULL 13/64] target-ppc: add maddld instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org Cc: agraf@suse.de, thuth@redhat.com, lvivier@redhat.com, benh@kernel.crashing.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Nikunj A Dadhania , David Gibson From: Nikunj A Dadhania maddld: Multiply-Add Low Doubleword Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the lower dword in the target register(RT). Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target-ppc/translate.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 1384fb7..488a105 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7740,6 +7740,17 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) GEN_VAFORM_PAIRED(vsel, vperm, 21) GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) +#if defined(TARGET_PPC64) +static void gen_maddld(DisasContext *ctx) +{ + TCGv_i64 t1 = tcg_temp_new_i64(); + + tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); + tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); + tcg_temp_free_i64(t1); +} +#endif /* defined(TARGET_PPC64) */ + GEN_VXFORM_NOA(vclzb, 1, 28) GEN_VXFORM_NOA(vclzh, 1, 29) GEN_VXFORM_NOA(vclzw, 1, 30) @@ -10355,6 +10366,9 @@ GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), +#if defined(TARGET_PPC64) +GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), +#endif GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), -- 2.7.4