From mboxrd@z Thu Jan 1 00:00:00 1970 From: Raju Lakkaraju Subject: [PATCH v2 net-next 2/2] net: phy: Add MAC-IF driver for Microsemi PHYs. Date: Thu, 8 Sep 2016 14:47:22 +0530 Message-ID: <1473326242-4198-3-git-send-email-Raju.Lakkaraju@microsemi.com> References: <20160824125934.GC13406@lunn.ch> <1473326242-4198-1-git-send-email-Raju.Lakkaraju@microsemi.com> Mime-Version: 1.0 Content-Type: text/plain Cc: , , , Raju Lakkaraju To: Return-path: Received: from mail-sn1nam01on0089.outbound.protection.outlook.com ([104.47.32.89]:24288 "EHLO NAM01-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S938787AbcIHJR5 (ORCPT ); Thu, 8 Sep 2016 05:17:57 -0400 In-Reply-To: <1473326242-4198-1-git-send-email-Raju.Lakkaraju@microsemi.com> Sender: netdev-owner@vger.kernel.org List-ID: From: Raju Lakkaraju Used Device Tree to configure the MAC Interface as per review comments and re-sending code for review Signed-off-by: Raju Lakkaraju --- drivers/net/phy/mscc.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c index f0a0e8d..dfbf4f3 100644 --- a/drivers/net/phy/mscc.c +++ b/drivers/net/phy/mscc.c @@ -24,6 +24,16 @@ enum rgmii_rx_clock_delay { RGMII_RX_CLK_DELAY_3_4_NS = 7 }; +/* Microsemi VSC85xx PHY registers */ +/* IEEE 802. Std Registers */ +#define MSCC_PHY_EXT_PHY_CNTL_1 23 +#define MAC_IF_SELECTION_MASK 0x1800 +#define MAC_IF_SELECTION_GMII 0 +#define MAC_IF_SELECTION_RMII 1 +#define MAC_IF_SELECTION_RGMII 2 +#define MAC_IF_SELECTION_POS 11 +#define FAR_END_LOOPBACK_MODE_MASK 0x0008 + #define MII_VSC85XX_INT_MASK 25 #define MII_VSC85XX_INT_MASK_MASK 0xa000 #define MII_VSC85XX_INT_STATUS 26 @@ -59,6 +69,52 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page) return rc; } +static int vsc85xx_soft_reset(struct phy_device *phydev) +{ + int rc; + u16 reg_val; + + reg_val = phy_read(phydev, MII_BMCR); + reg_val |= BMCR_RESET; + rc = phy_write(phydev, MII_BMCR, reg_val); + + return rc; +} + +static int vsc85xx_mac_if_set(struct phy_device *phydev, + phy_interface_t interface) +{ + int rc; + u16 reg_val; + + mutex_lock(&phydev->lock); + reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); + reg_val &= ~(MAC_IF_SELECTION_MASK); + switch (interface) { + case PHY_INTERFACE_MODE_RGMII: + reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS); + break; + case PHY_INTERFACE_MODE_RMII: + reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS); + break; + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + default: + reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS); + break; + } + rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); + if (rc != 0) + goto out_unlock; + + rc = vsc85xx_soft_reset(phydev); + +out_unlock: + mutex_unlock(&phydev->lock); + + return rc; +} + static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) { @@ -153,6 +209,10 @@ static int vsc85xx_config_init(struct phy_device *phydev) if (rc) return rc; + rc = vsc85xx_mac_if_set(phydev, phydev->interface); + if (rc) + return rc; + rc = genphy_config_init(phydev); return rc; -- 2.7.4