From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965789AbcIHOKp (ORCPT ); Thu, 8 Sep 2016 10:10:45 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:2339 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S933313AbcIHOKn (ORCPT ); Thu, 8 Sep 2016 10:10:43 -0400 Message-ID: <1473343836.1896.17.camel@mtkswgap22> Subject: Re: [PATCH 3/4] arm64: dts: mediatek: add mt6797 support From: Mars Cheng To: Marc Zyngier CC: Matthias Brugger , Rob Herring , Mark Rutland , "Michael Turquette" , Stephen Boyd , Erin Lo , James Liao , , CC Hwang , Loda Choui , Miles Chen , Scott Shu , Jades Shih , "Yingjoe Chen" , My Chuang , , , , Date: Thu, 8 Sep 2016 22:10:36 +0800 In-Reply-To: <57D16470.6050100@arm.com> References: <1473331794-27542-1-git-send-email-mars.cheng@mediatek.com> <1473331794-27542-4-git-send-email-mars.cheng@mediatek.com> <57D16470.6050100@arm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2016-09-08 at 14:15 +0100, Marc Zyngier wrote: > On 08/09/16 11:49, Mars Cheng wrote: > > This adds basic chip support for MT6797 SoC. > > > > Signed-off-by: Mars Cheng > > --- [...] > > > + gic: interrupt-controller@19000000 { > > + compatible = "arm,gic-v3"; > > + #interrupt-cells = <3>; > > + interrupt-parent = <&gic>; > > + interrupts = ; > > + interrupt-controller; > > + reg = <0 0x19000000 0 0x10000>, /* GICD */ > > + <0 0x19200000 0 0x200000>, /* GICR */ > > + <0 0x10240000 0 0x2000>; /* GICC */ > > Where are the GICV and GICH regions? No ITS? Have confirmed with our HW guys, there is no GICV, GICH, nor ITS in our GIC design. Thanks. > > Thanks, > > M. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mars Cheng Subject: Re: [PATCH 3/4] arm64: dts: mediatek: add mt6797 support Date: Thu, 8 Sep 2016 22:10:36 +0800 Message-ID: <1473343836.1896.17.camel@mtkswgap22> References: <1473331794-27542-1-git-send-email-mars.cheng@mediatek.com> <1473331794-27542-4-git-send-email-mars.cheng@mediatek.com> <57D16470.6050100@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <57D16470.6050100@arm.com> Sender: linux-clk-owner@vger.kernel.org To: Marc Zyngier Cc: Matthias Brugger , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd , Erin Lo , James Liao , linux-clk@vger.kernel.org, CC Hwang , Loda Choui , Miles Chen , Scott Shu , Jades Shih , Yingjoe Chen , My Chuang , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wsd_upstream@mediatek.com List-Id: devicetree@vger.kernel.org On Thu, 2016-09-08 at 14:15 +0100, Marc Zyngier wrote: > On 08/09/16 11:49, Mars Cheng wrote: > > This adds basic chip support for MT6797 SoC. > > > > Signed-off-by: Mars Cheng > > --- [...] > > > + gic: interrupt-controller@19000000 { > > + compatible = "arm,gic-v3"; > > + #interrupt-cells = <3>; > > + interrupt-parent = <&gic>; > > + interrupts = ; > > + interrupt-controller; > > + reg = <0 0x19000000 0 0x10000>, /* GICD */ > > + <0 0x19200000 0 0x200000>, /* GICR */ > > + <0 0x10240000 0 0x2000>; /* GICC */ > > Where are the GICV and GICH regions? No ITS? Have confirmed with our HW guys, there is no GICV, GICH, nor ITS in our GIC design. Thanks. > > Thanks, > > M.