From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44471) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi7s8-00034o-VT for qemu-devel@nongnu.org; Thu, 08 Sep 2016 18:32:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bi7s4-0000ck-QP for qemu-devel@nongnu.org; Thu, 08 Sep 2016 18:32:39 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:34863) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi7s4-0000cB-JK for qemu-devel@nongnu.org; Thu, 08 Sep 2016 18:32:36 -0400 Received: by mail-wm0-x242.google.com with SMTP id a6so200277wmc.2 for ; Thu, 08 Sep 2016 15:32:35 -0700 (PDT) From: Michael Rolnik Date: Fri, 9 Sep 2016 01:31:41 +0300 Message-Id: <1473373930-31547-1-git-send-email-mrolnik@gmail.com> Subject: [Qemu-devel] [PATCH RFC v1 00/29] ARC cores List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Michael Rolnik This series of patches adds ARC target to QEMU. It indends to support - ARCtangent-A5 processor - ARC 600 processor - ARC 700 processor All instructions except ASLS are implemented. Not fully tested yet. However I was able to execute correctly recursive fibonacci calculation. Reset vector is assumed to be some hardcoded value which worked for my test. I am planning to get FreeRTOS for ARC, once I get it, I will able to verify and complete interrupt support. Michael Rolnik (29): target-arc: initial commit target-arc: ADC, ADD, ADD1, ADD2, ADD3 target-arc: SUB, SUB1, SUB2, SUB3, SBC, RSUB, CMP target-arc: AND, OR, XOR, BIC, TST target-arc: ASL(m), ASR(m), LSR(m), ROR(m) target-arc: EX, LD, ST, SYNC, PREFETCH target-arc: MAX, MIN target-arc: MOV, EXT, SEX, SWAP target-arc: NEG, ABS, NOT target-arc: POP, PUSH target-arc: BCLR, BMSK, BSET, BTST, BXOR target-arc: RLC, RRC target-arc: NORM, NORMW target-arc: MPY, MPYH, MPYHU, MPYU target-arc: MUL64, MULU64, DIVAW target-arc: BBIT0, BBIT1, BR target-arc: B, BL target-arc: J, JL target-arc: LR, SR target-arc: ADDS, ADDSDW, SUBS, SUBSDW target-arc: ABSS, ABSSW, NEGS, NEGSW, RND16, SAT16 target-arc: ASLS, ASRS target-arc: FLAG, BRK, SLEEP target-arc: NOP, UNIMP target-arc: TRAP, SWI target-arc: RTIE target-arc: LP target-arc: decode target-arc: sample board .gitignore | 2 + MAINTAINERS | 6 + arch_init.c | 2 + configure | 5 + default-configs/arc-softmmu.mak | 0 hw/arc/Makefile.objs | 21 + hw/arc/sample.c | 80 ++ include/sysemu/arch_init.h | 1 + target-arc/Makefile.objs | 28 + target-arc/cpu-qom.h | 84 ++ target-arc/cpu.c | 269 ++++ target-arc/cpu.h | 174 +++ target-arc/decode.c | 2212 ++++++++++++++++++++++++++++++ target-arc/gdbstub.c | 138 ++ target-arc/helper.c | 74 + target-arc/helper.h | 29 + target-arc/machine.c | 35 + target-arc/machine.h | 21 + target-arc/op_helper.c | 443 ++++++ target-arc/translate-inst.c | 2855 +++++++++++++++++++++++++++++++++++++++ target-arc/translate-inst.h | 175 +++ target-arc/translate.c | 424 ++++++ target-arc/translate.h | 223 +++ 23 files changed, 7301 insertions(+) create mode 100644 default-configs/arc-softmmu.mak create mode 100644 hw/arc/Makefile.objs create mode 100644 hw/arc/sample.c create mode 100644 target-arc/Makefile.objs create mode 100644 target-arc/cpu-qom.h create mode 100644 target-arc/cpu.c create mode 100644 target-arc/cpu.h create mode 100644 target-arc/decode.c create mode 100644 target-arc/gdbstub.c create mode 100644 target-arc/helper.c create mode 100644 target-arc/helper.h create mode 100644 target-arc/machine.c create mode 100644 target-arc/machine.h create mode 100644 target-arc/op_helper.c create mode 100644 target-arc/translate-inst.c create mode 100644 target-arc/translate-inst.h create mode 100644 target-arc/translate.c create mode 100644 target-arc/translate.h -- 2.4.9 (Apple Git-60)