From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44641) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi7sM-0003Bu-57 for qemu-devel@nongnu.org; Thu, 08 Sep 2016 18:32:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bi7sK-0000jO-6C for qemu-devel@nongnu.org; Thu, 08 Sep 2016 18:32:53 -0400 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:36711) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi7sJ-0000j2-Vg for qemu-devel@nongnu.org; Thu, 08 Sep 2016 18:32:52 -0400 Received: by mail-wm0-x244.google.com with SMTP id l65so194259wmf.3 for ; Thu, 08 Sep 2016 15:32:51 -0700 (PDT) From: Michael Rolnik Date: Fri, 9 Sep 2016 01:31:53 +0300 Message-Id: <1473373930-31547-13-git-send-email-mrolnik@gmail.com> In-Reply-To: <1473373930-31547-1-git-send-email-mrolnik@gmail.com> References: <1473373930-31547-1-git-send-email-mrolnik@gmail.com> Subject: [Qemu-devel] [PATCH RFC v1 12/29] target-arc: RLC, RRC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Michael Rolnik Signed-off-by: Michael Rolnik --- target-arc/translate-inst.c | 57 +++++++++++++++++++++++++++++++++++++++++++++ target-arc/translate-inst.h | 2 ++ 2 files changed, 59 insertions(+) diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c index 91b7037..a0d601e 100644 --- a/target-arc/translate-inst.c +++ b/target-arc/translate-inst.c @@ -1308,3 +1308,60 @@ int arc_gen_BXOR(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) return BS_NONE; } +/* + RLC +*/ +int arc_gen_RLC(DisasCtxt *ctx, TCGv dest, TCGv src1) +{ + TCGv rslt = dest; + + if (TCGV_EQUAL(dest, src1)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_shli_tl(rslt, src1, 1); + tcg_gen_or_tl(rslt, rslt, cpu_Cf); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + tcg_gen_shri_tl(cpu_Cf, src1, 31); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + + return BS_NONE; +} + +/* + RRC +*/ +int arc_gen_RRC(DisasCtxt *ctx, TCGv dest, TCGv src1) +{ + TCGv rslt = dest; + + if (TCGV_EQUAL(dest, src1)) { + rslt = tcg_temp_new_i32(); + } + + tcg_gen_andi_tl(rslt, src1, 0xfffffffe); + tcg_gen_or_tl(rslt, rslt, cpu_Cf); + tcg_gen_rotri_tl(rslt, rslt, 1); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, rslt, 31); + tcg_gen_andi_tl(cpu_Cf, src1, 1); + } + + if (!TCGV_EQUAL(dest, rslt)) { + tcg_gen_mov_tl(dest, rslt); + tcg_temp_free_i32(rslt); + } + + return BS_NONE; +} + diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h index 88cae1c..5e1c52d 100644 --- a/target-arc/translate-inst.h +++ b/target-arc/translate-inst.h @@ -84,3 +84,5 @@ int arc_gen_BSET(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); int arc_gen_BTST(DisasCtxt *c, TCGv src1, TCGv src2); int arc_gen_BXOR(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_RRC(DisasCtxt *c, TCGv dest, TCGv src1); +int arc_gen_RLC(DisasCtxt *c, TCGv dest, TCGv src1); -- 2.4.9 (Apple Git-60)