From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi7sP-0003GF-E7 for qemu-devel@nongnu.org; Thu, 08 Sep 2016 18:32:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bi7sN-0000k4-CE for qemu-devel@nongnu.org; Thu, 08 Sep 2016 18:32:57 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:36715) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi7sN-0000jw-1x for qemu-devel@nongnu.org; Thu, 08 Sep 2016 18:32:55 -0400 Received: by mail-wm0-x242.google.com with SMTP id l65so194368wmf.3 for ; Thu, 08 Sep 2016 15:32:54 -0700 (PDT) From: Michael Rolnik Date: Fri, 9 Sep 2016 01:31:55 +0300 Message-Id: <1473373930-31547-15-git-send-email-mrolnik@gmail.com> In-Reply-To: <1473373930-31547-1-git-send-email-mrolnik@gmail.com> References: <1473373930-31547-1-git-send-email-mrolnik@gmail.com> Subject: [Qemu-devel] [PATCH RFC v1 14/29] target-arc: MPY, MPYH, MPYHU, MPYU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Michael Rolnik Signed-off-by: Michael Rolnik --- target-arc/translate-inst.c | 129 ++++++++++++++++++++++++++++++++++++++++++++ target-arc/translate-inst.h | 5 ++ 2 files changed, 134 insertions(+) diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c index 00785bf..92c75ac 100644 --- a/target-arc/translate-inst.c +++ b/target-arc/translate-inst.c @@ -1417,3 +1417,132 @@ int arc_gen_NORM(DisasCtxt *ctx, TCGv dest, TCGv src1) return BS_NONE; } +/* + MPY +*/ +int arc_gen_MPY(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv_i64 rslt = tcg_temp_new_i64(); + TCGv_i64 srcA = tcg_temp_new_i64(); + TCGv_i64 srcB = tcg_temp_new_i64(); + + tcg_gen_ext_i32_i64(srcA, src1); + tcg_gen_ext_i32_i64(srcB, src2); + + tcg_gen_mul_i64(rslt, srcA, srcB); + + tcg_gen_trunc_i64_tl(dest, rslt); + + if (ctx->opt.f) { + TCGv_i64 temp = tcg_temp_new_i64(); + + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, dest, ctx->zero); + + tcg_gen_trunc_i64_tl(cpu_Nf, rslt); + tcg_gen_shri_tl(cpu_Nf, cpu_Nf, 31); + + tcg_gen_ext_i32_i64(temp, dest); + tcg_gen_setcond_i64(TCG_COND_NE, temp, temp, rslt); + tcg_gen_trunc_i64_tl(cpu_Cf, temp); + + tcg_temp_free_i64(temp); + } + + tcg_temp_free_i64(rslt); + tcg_temp_free_i64(srcA); + tcg_temp_free_i64(srcB); + + return BS_NONE; +} + +/* + MPYH +*/ +int arc_gen_MPYH(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv_i64 rslt = tcg_temp_new_i64(); + TCGv_i64 srcA = tcg_temp_new_i64(); + TCGv_i64 srcB = tcg_temp_new_i64(); + + tcg_gen_ext_i32_i64(srcA, src1); + tcg_gen_ext_i32_i64(srcB, src2); + + tcg_gen_mul_i64(rslt, srcA, srcB); + + tcg_gen_sari_i64(rslt, rslt, 32); + tcg_gen_trunc_i64_tl(dest, rslt); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, dest, ctx->zero); + tcg_gen_shri_tl(cpu_Nf, dest, 31); + tcg_gen_movi_tl(cpu_Vf, 0); + } + + tcg_temp_free_i64(rslt); + tcg_temp_free_i64(srcA); + tcg_temp_free_i64(srcB); + + return BS_NONE; +} + +/* + MPYHU +*/ +int arc_gen_MPYHU(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv_i64 rslt = tcg_temp_new_i64(); + TCGv_i64 srcA = tcg_temp_new_i64(); + TCGv_i64 srcB = tcg_temp_new_i64(); + + tcg_gen_extu_i32_i64(srcA, src1); + tcg_gen_extu_i32_i64(srcB, src2); + + tcg_gen_mul_i64(rslt, srcA, srcB); + + tcg_gen_shri_i64(rslt, rslt, 32); + tcg_gen_trunc_i64_tl(dest, rslt); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, dest, ctx->zero); + tcg_gen_movi_tl(cpu_Nf, 0); + tcg_gen_movi_tl(cpu_Vf, 0); + } + + tcg_temp_free_i64(rslt); + tcg_temp_free_i64(srcA); + tcg_temp_free_i64(srcB); + + return BS_NONE; +} + +/* + MPYU +*/ +int arc_gen_MPYU(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv_i64 rslt = tcg_temp_new_i64(); + TCGv_i64 srcA = tcg_temp_new_i64(); + TCGv_i64 srcB = tcg_temp_new_i64(); + + tcg_gen_extu_i32_i64(srcA, src1); + tcg_gen_extu_i32_i64(srcB, src2); + + tcg_gen_mul_i64(rslt, srcA, srcB); + + tcg_gen_trunc_i64_tl(dest, rslt); + + if (ctx->opt.f) { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, dest, ctx->zero); + tcg_gen_movi_tl(cpu_Nf, 0); + tcg_gen_shri_i64(rslt, rslt, 32); + tcg_gen_trunc_i64_tl(cpu_Vf, rslt); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_Vf, cpu_Vf, 0); + } + + tcg_temp_free_i64(rslt); + tcg_temp_free_i64(srcA); + tcg_temp_free_i64(srcB); + + return BS_NONE; +} + diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h index 811c914..084c282 100644 --- a/target-arc/translate-inst.h +++ b/target-arc/translate-inst.h @@ -90,3 +90,8 @@ int arc_gen_RLC(DisasCtxt *c, TCGv dest, TCGv src1); int arc_gen_NORMW(DisasCtxt *c, TCGv dest, TCGv src1); int arc_gen_NORM(DisasCtxt *c, TCGv dest, TCGv src1); +int arc_gen_MPY(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_MPYH(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_MPYHU(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); +int arc_gen_MPYU(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2); + -- 2.4.9 (Apple Git-60)