From mboxrd@z Thu Jan 1 00:00:00 1970 From: Zhihong Wang Subject: [PATCH v5 4/6] vhost: add desc prefetch Date: Thu, 8 Sep 2016 23:39:26 -0400 Message-ID: <1473392368-84903-5-git-send-email-zhihong.wang@intel.com> References: <1471319402-112998-1-git-send-email-zhihong.wang@intel.com> <1473392368-84903-1-git-send-email-zhihong.wang@intel.com> Cc: maxime.coquelin@redhat.com, yuanhan.liu@linux.intel.com, thomas.monjalon@6wind.com, Zhihong Wang To: dev@dpdk.org Return-path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id AB7136CC9 for ; Fri, 9 Sep 2016 12:47:25 +0200 (CEST) In-Reply-To: <1473392368-84903-1-git-send-email-zhihong.wang@intel.com> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds descriptor prefetch to hide cache access latency. Signed-off-by: Zhihong Wang --- lib/librte_vhost/virtio_net.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/librte_vhost/virtio_net.c b/lib/librte_vhost/virtio_net.c index 6f63968..b38f18f 100644 --- a/lib/librte_vhost/virtio_net.c +++ b/lib/librte_vhost/virtio_net.c @@ -302,6 +302,12 @@ rte_vhost_enqueue_burst(int vid, uint16_t queue_id, /* start enqueuing packets 1 by 1 */ avail_idx = *((volatile uint16_t *)&vq->avail->idx); while (pkt_left && avail_idx != vq->last_used_idx) { + /* prefetch the next desc */ + if (pkt_left > 1 && avail_idx != vq->last_used_idx + 1) + rte_prefetch0(&vq->desc[vq->avail->ring[ + (vq->last_used_idx + 1) & + (vq->size - 1)]]); + if (enqueue_packet(dev, vq, avail_idx, pkts[pkt_idx], is_mrg_rxbuf)) break; -- 2.7.4