[PATCH v5 0/9] Add STM32 EXTI interrupt controller support

[PATCH v5 0/9] Add STM32 EXTI interrupt controller support

[Alexandre TORGUE]

Hi,

This v5 fixes bad copy/paste inside stm32exti driver (spot by Jason), and remove
GPIOLIB_IRQCHIP config for stm32 pinctrl driver (Linus).

The series adds support to EXTI interrupt controller and GPIO IRQ support in
STM32 pinctrl driver.

The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, fallin or both edges. Each line can also
be masked independently.

Regards 

Alex

Changes since v4:
-----------------
 - Fix bad copy/paste in stm32 exti driver
 - Remove GPIOLIB_IRQCHIP config in stm32 pinctrl driver 

Changes since v3:
-----------------
 - Review domain dealloc/free irq in stm32 pinctrl driver
 - Review domain dealloc/free irq in stm32 exti driver
 - Fix remarks on coding style

Changes since v2:
-----------------
 - Define irq_chip for GPIO banks
 - Use hierarchical domain for GPIO banks
 - Improve search loop inside stm32_exti handler 
 - Rebased on top of v4.8-rc1

Changes since v1:
-----------------
 - Rebased on top of v4.6-rc1
 - Change variable name from virq to irq (Linus W.)


Alexandre TORGUE (9):
  Documentation: dt-bindings: Document STM32 EXTI controller bindings
  drivers: irqchip: Add STM32 external interrupts support
  ARM: STM32: Select external interrupts controller
  ARM: dts: Add EXTI controller node to stm32f429
  Documentation: dt-bindings: Add IRQ related properties of STM32
    pinctrl
  pinctrl: Add IRQ support to STM32 gpios
  ARM: dts: Add GPIO irq support to STM2F429
  ARM: dts: Declare push button as GPIO key on stm32f429 boards
  ARM: config: Enable GPIO Key driver in stm32_defconfig

 .../interrupt-controller/st,stm32-exti.txt         |  20 ++
 .../bindings/pinctrl/st,stm32-pinctrl.txt          |   3 +
 arch/arm/Kconfig                                   |   1 +
 arch/arm/boot/dts/stm32429i-eval.dts               |  18 ++
 arch/arm/boot/dts/stm32f429-disco.dts              |  13 ++
 arch/arm/boot/dts/stm32f429.dtsi                   |  10 +
 arch/arm/configs/stm32_defconfig                   |   6 +-
 drivers/irqchip/Kconfig                            |   4 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-stm32-exti.c                   | 202 +++++++++++++++++++++
 drivers/pinctrl/stm32/Kconfig                      |   1 +
 drivers/pinctrl/stm32/pinctrl-stm32.c              | 163 ++++++++++++++++-
 12 files changed, 440 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
 create mode 100644 drivers/irqchip/irq-stm32-exti.c

-- 
1.9.1

[PATCH v5 0/9] Add STM32 EXTI interrupt controller support

[Alexandre TORGUE]

Hi,

This v5 fixes bad copy/paste inside stm32exti driver (spot by Jason), and remove
GPIOLIB_IRQCHIP config for stm32 pinctrl driver (Linus).

The series adds support to EXTI interrupt controller and GPIO IRQ support in
STM32 pinctrl driver.

The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, fallin or both edges. Each line can also
be masked independently.

Regards 

Alex

Changes since v4:
-----------------
 - Fix bad copy/paste in stm32 exti driver
 - Remove GPIOLIB_IRQCHIP config in stm32 pinctrl driver 

Changes since v3:
-----------------
 - Review domain dealloc/free irq in stm32 pinctrl driver
 - Review domain dealloc/free irq in stm32 exti driver
 - Fix remarks on coding style

Changes since v2:
-----------------
 - Define irq_chip for GPIO banks
 - Use hierarchical domain for GPIO banks
 - Improve search loop inside stm32_exti handler 
 - Rebased on top of v4.8-rc1

Changes since v1:
-----------------
 - Rebased on top of v4.6-rc1
 - Change variable name from virq to irq (Linus W.)


Alexandre TORGUE (9):
  Documentation: dt-bindings: Document STM32 EXTI controller bindings
  drivers: irqchip: Add STM32 external interrupts support
  ARM: STM32: Select external interrupts controller
  ARM: dts: Add EXTI controller node to stm32f429
  Documentation: dt-bindings: Add IRQ related properties of STM32
    pinctrl
  pinctrl: Add IRQ support to STM32 gpios
  ARM: dts: Add GPIO irq support to STM2F429
  ARM: dts: Declare push button as GPIO key on stm32f429 boards
  ARM: config: Enable GPIO Key driver in stm32_defconfig

 .../interrupt-controller/st,stm32-exti.txt         |  20 ++
 .../bindings/pinctrl/st,stm32-pinctrl.txt          |   3 +
 arch/arm/Kconfig                                   |   1 +
 arch/arm/boot/dts/stm32429i-eval.dts               |  18 ++
 arch/arm/boot/dts/stm32f429-disco.dts              |  13 ++
 arch/arm/boot/dts/stm32f429.dtsi                   |  10 +
 arch/arm/configs/stm32_defconfig                   |   6 +-
 drivers/irqchip/Kconfig                            |   4 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-stm32-exti.c                   | 202 +++++++++++++++++++++
 drivers/pinctrl/stm32/Kconfig                      |   1 +
 drivers/pinctrl/stm32/pinctrl-stm32.c              | 163 ++++++++++++++++-
 12 files changed, 440 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
 create mode 100644 drivers/irqchip/irq-stm32-exti.c

-- 
1.9.1

[PATCH v5 0/9] Add STM32 EXTI interrupt controller support

[Alexandre TORGUE]

Hi,

This v5 fixes bad copy/paste inside stm32exti driver (spot by Jason), and remove
GPIOLIB_IRQCHIP config for stm32 pinctrl driver (Linus).

The series adds support to EXTI interrupt controller and GPIO IRQ support in
STM32 pinctrl driver.

The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, fallin or both edges. Each line can also
be masked independently.

Regards 

Alex

Changes since v4:
-----------------
 - Fix bad copy/paste in stm32 exti driver
 - Remove GPIOLIB_IRQCHIP config in stm32 pinctrl driver 

Changes since v3:
-----------------
 - Review domain dealloc/free irq in stm32 pinctrl driver
 - Review domain dealloc/free irq in stm32 exti driver
 - Fix remarks on coding style

Changes since v2:
-----------------
 - Define irq_chip for GPIO banks
 - Use hierarchical domain for GPIO banks
 - Improve search loop inside stm32_exti handler 
 - Rebased on top of v4.8-rc1

Changes since v1:
-----------------
 - Rebased on top of v4.6-rc1
 - Change variable name from virq to irq (Linus W.)


Alexandre TORGUE (9):
  Documentation: dt-bindings: Document STM32 EXTI controller bindings
  drivers: irqchip: Add STM32 external interrupts support
  ARM: STM32: Select external interrupts controller
  ARM: dts: Add EXTI controller node to stm32f429
  Documentation: dt-bindings: Add IRQ related properties of STM32
    pinctrl
  pinctrl: Add IRQ support to STM32 gpios
  ARM: dts: Add GPIO irq support to STM2F429
  ARM: dts: Declare push button as GPIO key on stm32f429 boards
  ARM: config: Enable GPIO Key driver in stm32_defconfig

 .../interrupt-controller/st,stm32-exti.txt         |  20 ++
 .../bindings/pinctrl/st,stm32-pinctrl.txt          |   3 +
 arch/arm/Kconfig                                   |   1 +
 arch/arm/boot/dts/stm32429i-eval.dts               |  18 ++
 arch/arm/boot/dts/stm32f429-disco.dts              |  13 ++
 arch/arm/boot/dts/stm32f429.dtsi                   |  10 +
 arch/arm/configs/stm32_defconfig                   |   6 +-
 drivers/irqchip/Kconfig                            |   4 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-stm32-exti.c                   | 202 +++++++++++++++++++++
 drivers/pinctrl/stm32/Kconfig                      |   1 +
 drivers/pinctrl/stm32/pinctrl-stm32.c              | 163 ++++++++++++++++-
 12 files changed, 440 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
 create mode 100644 drivers/irqchip/irq-stm32-exti.c

-- 
1.9.1

[PATCH v5 1/9] Documentation: dt-bindings: Document STM32 EXTI controller bindings

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
new file mode 100644
index 0000000..6e7703d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
@@ -0,0 +1,20 @@
+STM32 External Interrupt Controller
+
+Required properties:
+
+- compatible: Should be "st,stm32-exti"
+- reg: Specifies base physical address and size of the registers
+- interrupt-controller: Indentifies the node as an interrupt controller
+- #interrupt-cells: Specifies the number of cells to encode an interrupt
+  specifier, shall be 2
+- interrupts: interrupts references to primary interrupt controller
+
+Example:
+
+exti: interrupt-controller@40013c00 {
+	compatible = "st,stm32-exti";
+	interrupt-controller;
+	#interrupt-cells = <2>;
+	reg = <0x40013C00 0x400>;
+	interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
+};
-- 
1.9.1

[PATCH v5 1/9] Documentation: dt-bindings: Document STM32 EXTI controller bindings

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
new file mode 100644
index 0000000..6e7703d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
@@ -0,0 +1,20 @@
+STM32 External Interrupt Controller
+
+Required properties:
+
+- compatible: Should be "st,stm32-exti"
+- reg: Specifies base physical address and size of the registers
+- interrupt-controller: Indentifies the node as an interrupt controller
+- #interrupt-cells: Specifies the number of cells to encode an interrupt
+  specifier, shall be 2
+- interrupts: interrupts references to primary interrupt controller
+
+Example:
+
+exti: interrupt-controller at 40013c00 {
+	compatible = "st,stm32-exti";
+	interrupt-controller;
+	#interrupt-cells = <2>;
+	reg = <0x40013C00 0x400>;
+	interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
+};
-- 
1.9.1

[PATCH v5 1/9] Documentation: dt-bindings: Document STM32 EXTI controller bindings

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
new file mode 100644
index 0000000..6e7703d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
@@ -0,0 +1,20 @@
+STM32 External Interrupt Controller
+
+Required properties:
+
+- compatible: Should be "st,stm32-exti"
+- reg: Specifies base physical address and size of the registers
+- interrupt-controller: Indentifies the node as an interrupt controller
+- #interrupt-cells: Specifies the number of cells to encode an interrupt
+  specifier, shall be 2
+- interrupts: interrupts references to primary interrupt controller
+
+Example:
+
+exti: interrupt-controller@40013c00 {
+	compatible = "st,stm32-exti";
+	interrupt-controller;
+	#interrupt-cells = <2>;
+	reg = <0x40013C00 0x400>;
+	interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
+};
-- 
1.9.1

Re: [PATCH v5 1/9] Documentation: dt-bindings: Document STM32 EXTI controller bindings

[Rob Herring]

On Fri, Sep 09, 2016 at 04:41:56PM +0200, Alexandre TORGUE wrote:
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v5 1/9] Documentation: dt-bindings: Document STM32 EXTI controller bindings

[Rob Herring]

On Fri, Sep 09, 2016 at 04:41:56PM +0200, Alexandre TORGUE wrote:
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v5 1/9] Documentation: dt-bindings: Document STM32 EXTI controller bindings

[Rob Herring]

On Fri, Sep 09, 2016 at 04:41:56PM +0200, Alexandre TORGUE wrote:
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre TORGUE]

The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7f87289..bc62d1f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -264,3 +264,7 @@ config EZNPS_GIC
 	select IRQ_DOMAIN
 	help
 	  Support the EZchip NPS400 global interrupt controller
+
+config STM32_EXTI
+	bool
+	select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 4c203b6..96383b2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI)		+= irq-mvebu-odmi.o
 obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scfg-msi.o
 obj-$(CONFIG_EZNPS_GIC)			+= irq-eznps.o
 obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed-vic.o
+obj-$(CONFIG_STM32_EXTI) 		+= irq-stm32-exti.o
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
new file mode 100644
index 0000000..95e46ba
--- /dev/null
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include <linux/bitops.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define EXTI_IMR	0x0
+#define EXTI_EMR	0x4
+#define EXTI_RTSR	0x8
+#define EXTI_FTSR	0xc
+#define EXTI_SWIER	0x10
+#define EXTI_PR		0x14
+
+static void stm32_irq_handler(struct irq_desc *desc)
+{
+	struct irq_domain *domain = irq_desc_get_handler_data(desc);
+	struct irq_chip_generic *gc = domain->gc->gc[0];
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	unsigned long pending;
+	int n;
+
+	chained_irq_enter(chip, desc);
+
+	while ((pending = irq_reg_readl(gc, EXTI_PR))) {
+		for_each_set_bit(n, &pending, BITS_PER_LONG) {
+			generic_handle_irq(irq_find_mapping(domain, n));
+			irq_reg_writel(gc, BIT(n), EXTI_PR);
+		}
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+	int pin = data->hwirq;
+	u32 rtsr, ftsr;
+
+	irq_gc_lock(gc);
+
+	rtsr = irq_reg_readl(gc, EXTI_RTSR);
+	ftsr = irq_reg_readl(gc, EXTI_FTSR);
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		rtsr |= BIT(pin);
+		ftsr &= ~BIT(pin);
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		rtsr &= ~BIT(pin);
+		ftsr |= BIT(pin);
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		rtsr |= BIT(pin);
+		ftsr |= BIT(pin);
+		break;
+	default:
+		irq_gc_unlock(gc);
+		return -EINVAL;
+	}
+
+	irq_reg_writel(gc, rtsr, EXTI_RTSR);
+	irq_reg_writel(gc, ftsr, EXTI_FTSR);
+
+	irq_gc_unlock(gc);
+
+	return 0;
+}
+
+static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+	int pin = data->hwirq;
+	u32 emr;
+
+	irq_gc_lock(gc);
+
+	emr = irq_reg_readl(gc, EXTI_EMR);
+	if (on)
+		emr |= BIT(pin);
+	else
+		emr &= ~BIT(pin);
+	irq_reg_writel(gc, emr, EXTI_EMR);
+
+	irq_gc_unlock(gc);
+
+	return 0;
+}
+
+static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
+			    unsigned int nr_irqs, void *data)
+{
+	struct irq_chip_generic *gc = d->gc->gc[0];
+	struct irq_fwspec *fwspec = data;
+	irq_hw_number_t hwirq;
+
+	hwirq = fwspec->param[0];
+
+	irq_map_generic_chip(d, virq, hwirq);
+	irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
+			    handle_simple_irq, NULL, NULL);
+
+	return 0;
+}
+
+static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
+			    unsigned int nr_irqs)
+{
+	struct irq_data *data = irq_get_irq_data(virq);
+
+	irq_gc_mask_clr_bit(data->parent_data);
+	irq_domain_reset_irq_data(data);
+}
+
+struct irq_domain_ops irq_exti_domain_ops = {
+	.map	= irq_map_generic_chip,
+	.xlate	= irq_domain_xlate_onetwocell,
+	.alloc  = stm32_exti_alloc,
+	.free	= stm32_exti_free,
+};
+
+static int __init stm32_exti_init(struct device_node *node,
+				  struct device_node *parent)
+{
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+	int nr_irqs, nr_exti, ret, i;
+	struct irq_chip_generic *gc;
+	struct irq_domain *domain;
+	void *base;
+
+	base = of_iomap(node, 0);
+	if (!base) {
+		pr_err("%s: Unable to map registers\n", node->full_name);
+		return -ENOMEM;
+	}
+
+	/* Determine number of irqs supported */
+	writel_relaxed(~0UL, base + EXTI_RTSR);
+	nr_exti = fls(readl_relaxed(base + EXTI_RTSR));
+	writel_relaxed(0, base + EXTI_RTSR);
+
+	pr_info("%s: %d External IRQs detected\n", node->full_name, nr_exti);
+
+	domain = irq_domain_add_linear(node, nr_exti,
+				       &irq_exti_domain_ops, NULL);
+	if (!domain) {
+		pr_err("%s: Could not register interrupt domain.\n",
+				node->name);
+		ret = -ENOMEM;
+		goto out_unmap;
+	}
+
+	ret = irq_alloc_domain_generic_chips(domain, nr_exti, 1, "exti",
+					     handle_edge_irq, clr, 0, 0);
+	if (ret) {
+		pr_err("%s: Could not allocate generic interrupt chip.\n",
+			node->full_name);
+		goto out_free_domain;
+	}
+
+	gc = domain->gc->gc[0];
+	gc->reg_base                         = base;
+	gc->chip_types->type               = IRQ_TYPE_EDGE_BOTH;
+	gc->chip_types->chip.name          = gc->chip_types[0].chip.name;
+	gc->chip_types->chip.irq_ack       = irq_gc_ack_set_bit;
+	gc->chip_types->chip.irq_mask      = irq_gc_mask_clr_bit;
+	gc->chip_types->chip.irq_unmask    = irq_gc_mask_set_bit;
+	gc->chip_types->chip.irq_set_type  = stm32_irq_set_type;
+	gc->chip_types->chip.irq_set_wake  = stm32_irq_set_wake;
+	gc->chip_types->regs.ack           = EXTI_PR;
+	gc->chip_types->regs.mask          = EXTI_IMR;
+	gc->chip_types->handler            = handle_edge_irq;
+
+	nr_irqs = of_irq_count(node);
+	for (i = 0; i < nr_irqs; i++) {
+		unsigned int irq = irq_of_parse_and_map(node, i);
+
+		irq_set_handler_data(irq, domain);
+		irq_set_chained_handler(irq, stm32_irq_handler);
+	}
+
+	return 0;
+
+out_free_domain:
+	irq_domain_remove(domain);
+out_unmap:
+	iounmap(base);
+	return ret;
+}
+
+IRQCHIP_DECLARE(stm32_exti, "st,stm32-exti", stm32_exti_init);
-- 
1.9.1

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre TORGUE]

The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7f87289..bc62d1f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -264,3 +264,7 @@ config EZNPS_GIC
 	select IRQ_DOMAIN
 	help
 	  Support the EZchip NPS400 global interrupt controller
+
+config STM32_EXTI
+	bool
+	select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 4c203b6..96383b2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI)		+= irq-mvebu-odmi.o
 obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scfg-msi.o
 obj-$(CONFIG_EZNPS_GIC)			+= irq-eznps.o
 obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed-vic.o
+obj-$(CONFIG_STM32_EXTI) 		+= irq-stm32-exti.o
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
new file mode 100644
index 0000000..95e46ba
--- /dev/null
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include <linux/bitops.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define EXTI_IMR	0x0
+#define EXTI_EMR	0x4
+#define EXTI_RTSR	0x8
+#define EXTI_FTSR	0xc
+#define EXTI_SWIER	0x10
+#define EXTI_PR		0x14
+
+static void stm32_irq_handler(struct irq_desc *desc)
+{
+	struct irq_domain *domain = irq_desc_get_handler_data(desc);
+	struct irq_chip_generic *gc = domain->gc->gc[0];
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	unsigned long pending;
+	int n;
+
+	chained_irq_enter(chip, desc);
+
+	while ((pending = irq_reg_readl(gc, EXTI_PR))) {
+		for_each_set_bit(n, &pending, BITS_PER_LONG) {
+			generic_handle_irq(irq_find_mapping(domain, n));
+			irq_reg_writel(gc, BIT(n), EXTI_PR);
+		}
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+	int pin = data->hwirq;
+	u32 rtsr, ftsr;
+
+	irq_gc_lock(gc);
+
+	rtsr = irq_reg_readl(gc, EXTI_RTSR);
+	ftsr = irq_reg_readl(gc, EXTI_FTSR);
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		rtsr |= BIT(pin);
+		ftsr &= ~BIT(pin);
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		rtsr &= ~BIT(pin);
+		ftsr |= BIT(pin);
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		rtsr |= BIT(pin);
+		ftsr |= BIT(pin);
+		break;
+	default:
+		irq_gc_unlock(gc);
+		return -EINVAL;
+	}
+
+	irq_reg_writel(gc, rtsr, EXTI_RTSR);
+	irq_reg_writel(gc, ftsr, EXTI_FTSR);
+
+	irq_gc_unlock(gc);
+
+	return 0;
+}
+
+static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+	int pin = data->hwirq;
+	u32 emr;
+
+	irq_gc_lock(gc);
+
+	emr = irq_reg_readl(gc, EXTI_EMR);
+	if (on)
+		emr |= BIT(pin);
+	else
+		emr &= ~BIT(pin);
+	irq_reg_writel(gc, emr, EXTI_EMR);
+
+	irq_gc_unlock(gc);
+
+	return 0;
+}
+
+static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
+			    unsigned int nr_irqs, void *data)
+{
+	struct irq_chip_generic *gc = d->gc->gc[0];
+	struct irq_fwspec *fwspec = data;
+	irq_hw_number_t hwirq;
+
+	hwirq = fwspec->param[0];
+
+	irq_map_generic_chip(d, virq, hwirq);
+	irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
+			    handle_simple_irq, NULL, NULL);
+
+	return 0;
+}
+
+static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
+			    unsigned int nr_irqs)
+{
+	struct irq_data *data = irq_get_irq_data(virq);
+
+	irq_gc_mask_clr_bit(data->parent_data);
+	irq_domain_reset_irq_data(data);
+}
+
+struct irq_domain_ops irq_exti_domain_ops = {
+	.map	= irq_map_generic_chip,
+	.xlate	= irq_domain_xlate_onetwocell,
+	.alloc  = stm32_exti_alloc,
+	.free	= stm32_exti_free,
+};
+
+static int __init stm32_exti_init(struct device_node *node,
+				  struct device_node *parent)
+{
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+	int nr_irqs, nr_exti, ret, i;
+	struct irq_chip_generic *gc;
+	struct irq_domain *domain;
+	void *base;
+
+	base = of_iomap(node, 0);
+	if (!base) {
+		pr_err("%s: Unable to map registers\n", node->full_name);
+		return -ENOMEM;
+	}
+
+	/* Determine number of irqs supported */
+	writel_relaxed(~0UL, base + EXTI_RTSR);
+	nr_exti = fls(readl_relaxed(base + EXTI_RTSR));
+	writel_relaxed(0, base + EXTI_RTSR);
+
+	pr_info("%s: %d External IRQs detected\n", node->full_name, nr_exti);
+
+	domain = irq_domain_add_linear(node, nr_exti,
+				       &irq_exti_domain_ops, NULL);
+	if (!domain) {
+		pr_err("%s: Could not register interrupt domain.\n",
+				node->name);
+		ret = -ENOMEM;
+		goto out_unmap;
+	}
+
+	ret = irq_alloc_domain_generic_chips(domain, nr_exti, 1, "exti",
+					     handle_edge_irq, clr, 0, 0);
+	if (ret) {
+		pr_err("%s: Could not allocate generic interrupt chip.\n",
+			node->full_name);
+		goto out_free_domain;
+	}
+
+	gc = domain->gc->gc[0];
+	gc->reg_base                         = base;
+	gc->chip_types->type               = IRQ_TYPE_EDGE_BOTH;
+	gc->chip_types->chip.name          = gc->chip_types[0].chip.name;
+	gc->chip_types->chip.irq_ack       = irq_gc_ack_set_bit;
+	gc->chip_types->chip.irq_mask      = irq_gc_mask_clr_bit;
+	gc->chip_types->chip.irq_unmask    = irq_gc_mask_set_bit;
+	gc->chip_types->chip.irq_set_type  = stm32_irq_set_type;
+	gc->chip_types->chip.irq_set_wake  = stm32_irq_set_wake;
+	gc->chip_types->regs.ack           = EXTI_PR;
+	gc->chip_types->regs.mask          = EXTI_IMR;
+	gc->chip_types->handler            = handle_edge_irq;
+
+	nr_irqs = of_irq_count(node);
+	for (i = 0; i < nr_irqs; i++) {
+		unsigned int irq = irq_of_parse_and_map(node, i);
+
+		irq_set_handler_data(irq, domain);
+		irq_set_chained_handler(irq, stm32_irq_handler);
+	}
+
+	return 0;
+
+out_free_domain:
+	irq_domain_remove(domain);
+out_unmap:
+	iounmap(base);
+	return ret;
+}
+
+IRQCHIP_DECLARE(stm32_exti, "st,stm32-exti", stm32_exti_init);
-- 
1.9.1

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre TORGUE]

The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7f87289..bc62d1f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -264,3 +264,7 @@ config EZNPS_GIC
 	select IRQ_DOMAIN
 	help
 	  Support the EZchip NPS400 global interrupt controller
+
+config STM32_EXTI
+	bool
+	select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 4c203b6..96383b2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI)		+= irq-mvebu-odmi.o
 obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scfg-msi.o
 obj-$(CONFIG_EZNPS_GIC)			+= irq-eznps.o
 obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed-vic.o
+obj-$(CONFIG_STM32_EXTI) 		+= irq-stm32-exti.o
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
new file mode 100644
index 0000000..95e46ba
--- /dev/null
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include <linux/bitops.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define EXTI_IMR	0x0
+#define EXTI_EMR	0x4
+#define EXTI_RTSR	0x8
+#define EXTI_FTSR	0xc
+#define EXTI_SWIER	0x10
+#define EXTI_PR		0x14
+
+static void stm32_irq_handler(struct irq_desc *desc)
+{
+	struct irq_domain *domain = irq_desc_get_handler_data(desc);
+	struct irq_chip_generic *gc = domain->gc->gc[0];
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	unsigned long pending;
+	int n;
+
+	chained_irq_enter(chip, desc);
+
+	while ((pending = irq_reg_readl(gc, EXTI_PR))) {
+		for_each_set_bit(n, &pending, BITS_PER_LONG) {
+			generic_handle_irq(irq_find_mapping(domain, n));
+			irq_reg_writel(gc, BIT(n), EXTI_PR);
+		}
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+	int pin = data->hwirq;
+	u32 rtsr, ftsr;
+
+	irq_gc_lock(gc);
+
+	rtsr = irq_reg_readl(gc, EXTI_RTSR);
+	ftsr = irq_reg_readl(gc, EXTI_FTSR);
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		rtsr |= BIT(pin);
+		ftsr &= ~BIT(pin);
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		rtsr &= ~BIT(pin);
+		ftsr |= BIT(pin);
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		rtsr |= BIT(pin);
+		ftsr |= BIT(pin);
+		break;
+	default:
+		irq_gc_unlock(gc);
+		return -EINVAL;
+	}
+
+	irq_reg_writel(gc, rtsr, EXTI_RTSR);
+	irq_reg_writel(gc, ftsr, EXTI_FTSR);
+
+	irq_gc_unlock(gc);
+
+	return 0;
+}
+
+static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+	int pin = data->hwirq;
+	u32 emr;
+
+	irq_gc_lock(gc);
+
+	emr = irq_reg_readl(gc, EXTI_EMR);
+	if (on)
+		emr |= BIT(pin);
+	else
+		emr &= ~BIT(pin);
+	irq_reg_writel(gc, emr, EXTI_EMR);
+
+	irq_gc_unlock(gc);
+
+	return 0;
+}
+
+static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
+			    unsigned int nr_irqs, void *data)
+{
+	struct irq_chip_generic *gc = d->gc->gc[0];
+	struct irq_fwspec *fwspec = data;
+	irq_hw_number_t hwirq;
+
+	hwirq = fwspec->param[0];
+
+	irq_map_generic_chip(d, virq, hwirq);
+	irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
+			    handle_simple_irq, NULL, NULL);
+
+	return 0;
+}
+
+static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
+			    unsigned int nr_irqs)
+{
+	struct irq_data *data = irq_get_irq_data(virq);
+
+	irq_gc_mask_clr_bit(data->parent_data);
+	irq_domain_reset_irq_data(data);
+}
+
+struct irq_domain_ops irq_exti_domain_ops = {
+	.map	= irq_map_generic_chip,
+	.xlate	= irq_domain_xlate_onetwocell,
+	.alloc  = stm32_exti_alloc,
+	.free	= stm32_exti_free,
+};
+
+static int __init stm32_exti_init(struct device_node *node,
+				  struct device_node *parent)
+{
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+	int nr_irqs, nr_exti, ret, i;
+	struct irq_chip_generic *gc;
+	struct irq_domain *domain;
+	void *base;
+
+	base = of_iomap(node, 0);
+	if (!base) {
+		pr_err("%s: Unable to map registers\n", node->full_name);
+		return -ENOMEM;
+	}
+
+	/* Determine number of irqs supported */
+	writel_relaxed(~0UL, base + EXTI_RTSR);
+	nr_exti = fls(readl_relaxed(base + EXTI_RTSR));
+	writel_relaxed(0, base + EXTI_RTSR);
+
+	pr_info("%s: %d External IRQs detected\n", node->full_name, nr_exti);
+
+	domain = irq_domain_add_linear(node, nr_exti,
+				       &irq_exti_domain_ops, NULL);
+	if (!domain) {
+		pr_err("%s: Could not register interrupt domain.\n",
+				node->name);
+		ret = -ENOMEM;
+		goto out_unmap;
+	}
+
+	ret = irq_alloc_domain_generic_chips(domain, nr_exti, 1, "exti",
+					     handle_edge_irq, clr, 0, 0);
+	if (ret) {
+		pr_err("%s: Could not allocate generic interrupt chip.\n",
+			node->full_name);
+		goto out_free_domain;
+	}
+
+	gc = domain->gc->gc[0];
+	gc->reg_base                         = base;
+	gc->chip_types->type               = IRQ_TYPE_EDGE_BOTH;
+	gc->chip_types->chip.name          = gc->chip_types[0].chip.name;
+	gc->chip_types->chip.irq_ack       = irq_gc_ack_set_bit;
+	gc->chip_types->chip.irq_mask      = irq_gc_mask_clr_bit;
+	gc->chip_types->chip.irq_unmask    = irq_gc_mask_set_bit;
+	gc->chip_types->chip.irq_set_type  = stm32_irq_set_type;
+	gc->chip_types->chip.irq_set_wake  = stm32_irq_set_wake;
+	gc->chip_types->regs.ack           = EXTI_PR;
+	gc->chip_types->regs.mask          = EXTI_IMR;
+	gc->chip_types->handler            = handle_edge_irq;
+
+	nr_irqs = of_irq_count(node);
+	for (i = 0; i < nr_irqs; i++) {
+		unsigned int irq = irq_of_parse_and_map(node, i);
+
+		irq_set_handler_data(irq, domain);
+		irq_set_chained_handler(irq, stm32_irq_handler);
+	}
+
+	return 0;
+
+out_free_domain:
+	irq_domain_remove(domain);
+out_unmap:
+	iounmap(base);
+	return ret;
+}
+
+IRQCHIP_DECLARE(stm32_exti, "st,stm32-exti", stm32_exti_init);
-- 
1.9.1

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Marc Zyngier]

On 09/09/16 15:41, Alexandre TORGUE wrote:
> The STM32 external interrupt controller consists of edge detectors that
> generate interrupts requests or wake-up events.
> 
> Each line can be independently configured as interrupt or wake-up source,
> and triggers either on rising, falling or both edges. Each line can also
> be masked independently.
> 
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org>

Acked-by: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>

	M.
-- 
Jazz is not dead. It just smells funny...
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[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Marc Zyngier]

On 09/09/16 15:41, Alexandre TORGUE wrote:
> The STM32 external interrupt controller consists of edge detectors that
> generate interrupts requests or wake-up events.
> 
> Each line can be independently configured as interrupt or wake-up source,
> and triggers either on rising, falling or both edges. Each line can also
> be masked independently.
> 
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

Acked-by: Marc Zyngier <marc.zyngier@arm.com>

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Marc Zyngier]

On 09/09/16 15:41, Alexandre TORGUE wrote:
> The STM32 external interrupt controller consists of edge detectors that
> generate interrupts requests or wake-up events.
> 
> Each line can be independently configured as interrupt or wake-up source,
> and triggers either on rising, falling or both edges. Each line can also
> be masked independently.
> 
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

Acked-by: Marc Zyngier <marc.zyngier@arm.com>

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
> +static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
> +			    unsigned int nr_irqs)
> +{
> +	struct irq_data *data = irq_get_irq_data(virq);
> +
> +	irq_gc_mask_clr_bit(data->parent_data);

I have a hard time to understand this. The irq domain is not hierarchical.

> +	irq_domain_reset_irq_data(data);

> +	domain = irq_domain_add_linear(node, nr_exti,
> +				       &irq_exti_domain_ops, NULL);

It's a simple linear domain. So how can data->parent_data be a valid
irq_data pointer? Answer: It can't!

But it doesn't blow up in your face simply because the alloc/free callbacks
are never invoked for simple non hierarchical domains. So you should have
removed that stuff after copying some other irqchip driver.

Thanks,

	tglx

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
> +static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
> +			    unsigned int nr_irqs)
> +{
> +	struct irq_data *data = irq_get_irq_data(virq);
> +
> +	irq_gc_mask_clr_bit(data->parent_data);

I have a hard time to understand this. The irq domain is not hierarchical.

> +	irq_domain_reset_irq_data(data);

> +	domain = irq_domain_add_linear(node, nr_exti,
> +				       &irq_exti_domain_ops, NULL);

It's a simple linear domain. So how can data->parent_data be a valid
irq_data pointer? Answer: It can't!

But it doesn't blow up in your face simply because the alloc/free callbacks
are never invoked for simple non hierarchical domains. So you should have
removed that stuff after copying some other irqchip driver.

Thanks,

	tglx

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Hi Thomas,

On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
> On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
>> +static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
>> +			    unsigned int nr_irqs)
>> +{
>> +	struct irq_data *data = irq_get_irq_data(virq);
>> +
>> +	irq_gc_mask_clr_bit(data->parent_data);
>
> I have a hard time to understand this. The irq domain is not hierarchical.

Actually, I wanted to test ".free" callback function of gpio_irq_domain 
in STM32 pinctrl driver. To do that I modified gpio driver: just after 
getting virq through gpio_to_irq, I called "irq_dispose_mapping(virq)".
I know it is dirty but I thought it was the only way to test.

Doing that, I see that ".free" callback of gpio domain is called but as 
it is hirerchical ".free" callback for parent domain (exti one) is also 
called. I observed that virq was well unmapped, but not masked at exti 
level. It is for this reason than I added 
"irq_gc_mask_clr_bit(data->parent_data);" which mask interrupt at exti 
level.

Maybe this use case can never happen ? (and in this case all this stuff 
is not needed)

>
>> +	irq_domain_reset_irq_data(data);
>
>> +	domain = irq_domain_add_linear(node, nr_exti,
>> +				       &irq_exti_domain_ops, NULL);
>
> It's a simple linear domain. So how can data->parent_data be a valid
> irq_data pointer? Answer: It can't!

This Exti domain is parent of stm32 gpio domain. When ".free" callback 
of stm32 gpio domain is called then ".free" callback of Exti domain will 
be automatically called. Those both ".free" callbacks are called with 
"virq". This virq is created through stm32 gpio domain (in stm32 pinctrl 
driver), data and parent->data are then associated to it.

Sorry if it is not clear.

Regards

Alex

>
> But it doesn't blow up in your face simply because the alloc/free callbacks
> are never invoked for simple non hierarchical domains. So you should have
> removed that stuff after copying some other irqchip driver.



>
> Thanks,
>
> 	tglx
>

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Hi Thomas,

On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
> On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
>> +static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
>> +			    unsigned int nr_irqs)
>> +{
>> +	struct irq_data *data = irq_get_irq_data(virq);
>> +
>> +	irq_gc_mask_clr_bit(data->parent_data);
>
> I have a hard time to understand this. The irq domain is not hierarchical.

Actually, I wanted to test ".free" callback function of gpio_irq_domain 
in STM32 pinctrl driver. To do that I modified gpio driver: just after 
getting virq through gpio_to_irq, I called "irq_dispose_mapping(virq)".
I know it is dirty but I thought it was the only way to test.

Doing that, I see that ".free" callback of gpio domain is called but as 
it is hirerchical ".free" callback for parent domain (exti one) is also 
called. I observed that virq was well unmapped, but not masked at exti 
level. It is for this reason than I added 
"irq_gc_mask_clr_bit(data->parent_data);" which mask interrupt at exti 
level.

Maybe this use case can never happen ? (and in this case all this stuff 
is not needed)

>
>> +	irq_domain_reset_irq_data(data);
>
>> +	domain = irq_domain_add_linear(node, nr_exti,
>> +				       &irq_exti_domain_ops, NULL);
>
> It's a simple linear domain. So how can data->parent_data be a valid
> irq_data pointer? Answer: It can't!

This Exti domain is parent of stm32 gpio domain. When ".free" callback 
of stm32 gpio domain is called then ".free" callback of Exti domain will 
be automatically called. Those both ".free" callbacks are called with 
"virq". This virq is created through stm32 gpio domain (in stm32 pinctrl 
driver), data and parent->data are then associated to it.

Sorry if it is not clear.

Regards

Alex

>
> But it doesn't blow up in your face simply because the alloc/free callbacks
> are never invoked for simple non hierarchical domains. So you should have
> removed that stuff after copying some other irqchip driver.



>
> Thanks,
>
> 	tglx
>

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Hi Thomas,

On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
> On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
>> +static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
>> +			    unsigned int nr_irqs)
>> +{
>> +	struct irq_data *data = irq_get_irq_data(virq);
>> +
>> +	irq_gc_mask_clr_bit(data->parent_data);
>
> I have a hard time to understand this. The irq domain is not hierarchical.

Actually, I wanted to test ".free" callback function of gpio_irq_domain 
in STM32 pinctrl driver. To do that I modified gpio driver: just after 
getting virq through gpio_to_irq, I called "irq_dispose_mapping(virq)".
I know it is dirty but I thought it was the only way to test.

Doing that, I see that ".free" callback of gpio domain is called but as 
it is hirerchical ".free" callback for parent domain (exti one) is also 
called. I observed that virq was well unmapped, but not masked at exti 
level. It is for this reason than I added 
"irq_gc_mask_clr_bit(data->parent_data);" which mask interrupt at exti 
level.

Maybe this use case can never happen ? (and in this case all this stuff 
is not needed)

>
>> +	irq_domain_reset_irq_data(data);
>
>> +	domain = irq_domain_add_linear(node, nr_exti,
>> +				       &irq_exti_domain_ops, NULL);
>
> It's a simple linear domain. So how can data->parent_data be a valid
> irq_data pointer? Answer: It can't!

This Exti domain is parent of stm32 gpio domain. When ".free" callback 
of stm32 gpio domain is called then ".free" callback of Exti domain will 
be automatically called. Those both ".free" callbacks are called with 
"virq". This virq is created through stm32 gpio domain (in stm32 pinctrl 
driver), data and parent->data are then associated to it.

Sorry if it is not clear.

Regards

Alex

>
> But it doesn't blow up in your face simply because the alloc/free callbacks
> are never invoked for simple non hierarchical domains. So you should have
> removed that stuff after copying some other irqchip driver.



>
> Thanks,
>
> 	tglx
>

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Tue, 13 Sep 2016, Alexandre Torgue wrote:
> On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
> > On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
> > > +static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
> > > +			    unsigned int nr_irqs)
> > > +{
> > > +	struct irq_data *data = irq_get_irq_data(virq);
> > > +
> > > +	irq_gc_mask_clr_bit(data->parent_data);
> > 
> > I have a hard time to understand this. The irq domain is not hierarchical.
> 
> Actually, I wanted to test ".free" callback function of gpio_irq_domain in
> STM32 pinctrl driver. To do that I modified gpio driver: just after getting
> virq through gpio_to_irq, I called "irq_dispose_mapping(virq)".
> I know it is dirty but I thought it was the only way to test.
> 
> Doing that, I see that ".free" callback of gpio domain is called but as it is
> hirerchical ".free" callback for parent domain (exti one) is also called. I
> observed that virq was well unmapped, but not masked at exti level. It is for
> this reason than I added "irq_gc_mask_clr_bit(data->parent_data);" which mask
> interrupt at exti level.

Aargh. I really misread the patch, but this is entirely non obvious and you
should do:

       struct irq_data *data = irq_domain_get_irq_data(d, virq);

       irq_gc_mask_clr_bit(d);

Then it is entirely clear that you mask the interrupt of _this_ (the exti)
domain.

Now what really bugs me is that you do that at all. An interrupt which is
freed must be masked already. Why is it unmasked in the first place?

Thanks,

	tglx

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Tue, 13 Sep 2016, Alexandre Torgue wrote:
> On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
> > On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
> > > +static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
> > > +			    unsigned int nr_irqs)
> > > +{
> > > +	struct irq_data *data = irq_get_irq_data(virq);
> > > +
> > > +	irq_gc_mask_clr_bit(data->parent_data);
> > 
> > I have a hard time to understand this. The irq domain is not hierarchical.
> 
> Actually, I wanted to test ".free" callback function of gpio_irq_domain in
> STM32 pinctrl driver. To do that I modified gpio driver: just after getting
> virq through gpio_to_irq, I called "irq_dispose_mapping(virq)".
> I know it is dirty but I thought it was the only way to test.
> 
> Doing that, I see that ".free" callback of gpio domain is called but as it is
> hirerchical ".free" callback for parent domain (exti one) is also called. I
> observed that virq was well unmapped, but not masked at exti level. It is for
> this reason than I added "irq_gc_mask_clr_bit(data->parent_data);" which mask
> interrupt at exti level.

Aargh. I really misread the patch, but this is entirely non obvious and you
should do:

       struct irq_data *data = irq_domain_get_irq_data(d, virq);

       irq_gc_mask_clr_bit(d);

Then it is entirely clear that you mask the interrupt of _this_ (the exti)
domain.

Now what really bugs me is that you do that at all. An interrupt which is
freed must be masked already. Why is it unmasked in the first place?

Thanks,

	tglx

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Hi Thomas,

On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
> On Tue, 13 Sep 2016, Alexandre Torgue wrote:
>> On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
>>> On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
>>>> +static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
>>>> +			    unsigned int nr_irqs)
>>>> +{
>>>> +	struct irq_data *data = irq_get_irq_data(virq);
>>>> +
>>>> +	irq_gc_mask_clr_bit(data->parent_data);
>>>
>>> I have a hard time to understand this. The irq domain is not hierarchical.
>>
>> Actually, I wanted to test ".free" callback function of gpio_irq_domain in
>> STM32 pinctrl driver. To do that I modified gpio driver: just after getting
>> virq through gpio_to_irq, I called "irq_dispose_mapping(virq)".
>> I know it is dirty but I thought it was the only way to test.
>>
>> Doing that, I see that ".free" callback of gpio domain is called but as it is
>> hirerchical ".free" callback for parent domain (exti one) is also called. I
>> observed that virq was well unmapped, but not masked at exti level. It is for
>> this reason than I added "irq_gc_mask_clr_bit(data->parent_data);" which mask
>> interrupt at exti level.
>
> Aargh. I really misread the patch, but this is entirely non obvious and you
> should do:
>
>        struct irq_data *data = irq_domain_get_irq_data(d, virq);
>
>        irq_gc_mask_clr_bit(d);
>
> Then it is entirely clear that you mask the interrupt of _this_ (the exti)
> domain.

Ok, it's easier to understand like that.

>
> Now what really bugs me is that you do that at all. An interrupt which is
> freed must be masked already. Why is it unmasked in the first place?

Honestly I don't know. When "devm_free_irq" is called to release virq, 
there is no issue and interrupt is well masked. But, when I tried to use
"irq_dispose_mapping(virq)" I observed that .free is called (child and 
parent domain) but interrupt is not masked.

Regards

Alex

>
> Thanks,
>
> 	tglx
>

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Hi Thomas,

On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
> On Tue, 13 Sep 2016, Alexandre Torgue wrote:
>> On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
>>> On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
>>>> +static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
>>>> +			    unsigned int nr_irqs)
>>>> +{
>>>> +	struct irq_data *data = irq_get_irq_data(virq);
>>>> +
>>>> +	irq_gc_mask_clr_bit(data->parent_data);
>>>
>>> I have a hard time to understand this. The irq domain is not hierarchical.
>>
>> Actually, I wanted to test ".free" callback function of gpio_irq_domain in
>> STM32 pinctrl driver. To do that I modified gpio driver: just after getting
>> virq through gpio_to_irq, I called "irq_dispose_mapping(virq)".
>> I know it is dirty but I thought it was the only way to test.
>>
>> Doing that, I see that ".free" callback of gpio domain is called but as it is
>> hirerchical ".free" callback for parent domain (exti one) is also called. I
>> observed that virq was well unmapped, but not masked at exti level. It is for
>> this reason than I added "irq_gc_mask_clr_bit(data->parent_data);" which mask
>> interrupt at exti level.
>
> Aargh. I really misread the patch, but this is entirely non obvious and you
> should do:
>
>        struct irq_data *data = irq_domain_get_irq_data(d, virq);
>
>        irq_gc_mask_clr_bit(d);
>
> Then it is entirely clear that you mask the interrupt of _this_ (the exti)
> domain.

Ok, it's easier to understand like that.

>
> Now what really bugs me is that you do that at all. An interrupt which is
> freed must be masked already. Why is it unmasked in the first place?

Honestly I don't know. When "devm_free_irq" is called to release virq, 
there is no issue and interrupt is well masked. But, when I tried to use
"irq_dispose_mapping(virq)" I observed that .free is called (child and 
parent domain) but interrupt is not masked.

Regards

Alex

>
> Thanks,
>
> 	tglx
>

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Hi Thomas,

On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
> On Tue, 13 Sep 2016, Alexandre Torgue wrote:
>> On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
>>> On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
>>>> +static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
>>>> +			    unsigned int nr_irqs)
>>>> +{
>>>> +	struct irq_data *data = irq_get_irq_data(virq);
>>>> +
>>>> +	irq_gc_mask_clr_bit(data->parent_data);
>>>
>>> I have a hard time to understand this. The irq domain is not hierarchical.
>>
>> Actually, I wanted to test ".free" callback function of gpio_irq_domain in
>> STM32 pinctrl driver. To do that I modified gpio driver: just after getting
>> virq through gpio_to_irq, I called "irq_dispose_mapping(virq)".
>> I know it is dirty but I thought it was the only way to test.
>>
>> Doing that, I see that ".free" callback of gpio domain is called but as it is
>> hirerchical ".free" callback for parent domain (exti one) is also called. I
>> observed that virq was well unmapped, but not masked at exti level. It is for
>> this reason than I added "irq_gc_mask_clr_bit(data->parent_data);" which mask
>> interrupt at exti level.
>
> Aargh. I really misread the patch, but this is entirely non obvious and you
> should do:
>
>        struct irq_data *data = irq_domain_get_irq_data(d, virq);
>
>        irq_gc_mask_clr_bit(d);
>
> Then it is entirely clear that you mask the interrupt of _this_ (the exti)
> domain.

Ok, it's easier to understand like that.

>
> Now what really bugs me is that you do that at all. An interrupt which is
> freed must be masked already. Why is it unmasked in the first place?

Honestly I don't know. When "devm_free_irq" is called to release virq, 
there is no issue and interrupt is well masked. But, when I tried to use
"irq_dispose_mapping(virq)" I observed that .free is called (child and 
parent domain) but interrupt is not masked.

Regards

Alex

>
> Thanks,
>
> 	tglx
>

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Wed, 14 Sep 2016, Alexandre Torgue wrote:
> On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
> > 
> > Now what really bugs me is that you do that at all. An interrupt which is
> > freed must be masked already. Why is it unmasked in the first place?
> 
> Honestly I don't know. When "devm_free_irq" is called to release virq, there
> is no issue and interrupt is well masked. But, when I tried to use
> "irq_dispose_mapping(virq)" I observed that .free is called (child and parent
> domain) but interrupt is not masked.

Well, you just used some function in some context which is not relevant to
the normal operation. So adding that mask() is just paranoia for no value.

Thanks,

	tglx

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Wed, 14 Sep 2016, Alexandre Torgue wrote:
> On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
> > 
> > Now what really bugs me is that you do that at all. An interrupt which is
> > freed must be masked already. Why is it unmasked in the first place?
> 
> Honestly I don't know. When "devm_free_irq" is called to release virq, there
> is no issue and interrupt is well masked. But, when I tried to use
> "irq_dispose_mapping(virq)" I observed that .free is called (child and parent
> domain) but interrupt is not masked.

Well, you just used some function in some context which is not relevant to
the normal operation. So adding that mask() is just paranoia for no value.

Thanks,

	tglx

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
> On Wed, 14 Sep 2016, Alexandre Torgue wrote:
>> On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
>>>
>>> Now what really bugs me is that you do that at all. An interrupt which is
>>> freed must be masked already. Why is it unmasked in the first place?
>>
>> Honestly I don't know. When "devm_free_irq" is called to release virq, there
>> is no issue and interrupt is well masked. But, when I tried to use
>> "irq_dispose_mapping(virq)" I observed that .free is called (child and parent
>> domain) but interrupt is not masked.
>
> Well, you just used some function in some context which is not relevant to
> the normal operation. So adding that mask() is just paranoia for no value.

I agree. I just wanted to "force" a test for .free callback. If it not 
relevant I'll remove ".free" callback of exti domain.
As a part of this series has already been taken by Linus (pinctrl part), 
I will send a new series only for irqchip part (patches [1] and [2]). Do 
you agree ?

Thanks
Alex


>
> Thanks,
>
> 	tglx
>

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
> On Wed, 14 Sep 2016, Alexandre Torgue wrote:
>> On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
>>>
>>> Now what really bugs me is that you do that at all. An interrupt which is
>>> freed must be masked already. Why is it unmasked in the first place?
>>
>> Honestly I don't know. When "devm_free_irq" is called to release virq, there
>> is no issue and interrupt is well masked. But, when I tried to use
>> "irq_dispose_mapping(virq)" I observed that .free is called (child and parent
>> domain) but interrupt is not masked.
>
> Well, you just used some function in some context which is not relevant to
> the normal operation. So adding that mask() is just paranoia for no value.

I agree. I just wanted to "force" a test for .free callback. If it not 
relevant I'll remove ".free" callback of exti domain.
As a part of this series has already been taken by Linus (pinctrl part), 
I will send a new series only for irqchip part (patches [1] and [2]). Do 
you agree ?

Thanks
Alex


>
> Thanks,
>
> 	tglx
>

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
> On Wed, 14 Sep 2016, Alexandre Torgue wrote:
>> On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
>>>
>>> Now what really bugs me is that you do that at all. An interrupt which is
>>> freed must be masked already. Why is it unmasked in the first place?
>>
>> Honestly I don't know. When "devm_free_irq" is called to release virq, there
>> is no issue and interrupt is well masked. But, when I tried to use
>> "irq_dispose_mapping(virq)" I observed that .free is called (child and parent
>> domain) but interrupt is not masked.
>
> Well, you just used some function in some context which is not relevant to
> the normal operation. So adding that mask() is just paranoia for no value.

I agree. I just wanted to "force" a test for .free callback. If it not 
relevant I'll remove ".free" callback of exti domain.
As a part of this series has already been taken by Linus (pinctrl part), 
I will send a new series only for irqchip part (patches [1] and [2]). Do 
you agree ?

Thanks
Alex


>
> Thanks,
>
> 	tglx
>

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Hi Thomas,

On 09/14/2016 03:44 PM, Alexandre Torgue wrote:
>
>
> On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
>> On Wed, 14 Sep 2016, Alexandre Torgue wrote:
>>> On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
>>>>
>>>> Now what really bugs me is that you do that at all. An interrupt
>>>> which is
>>>> freed must be masked already. Why is it unmasked in the first place?
>>>
>>> Honestly I don't know. When "devm_free_irq" is called to release
>>> virq, there
>>> is no issue and interrupt is well masked. But, when I tried to use
>>> "irq_dispose_mapping(virq)" I observed that .free is called (child
>>> and parent
>>> domain) but interrupt is not masked.
>>
>> Well, you just used some function in some context which is not
>> relevant to
>> the normal operation. So adding that mask() is just paranoia for no
>> value.
>
A gentle reminder ping...
If ".free" callback is not relevant then I 'll remove it from exti domain.

> I agree. I just wanted to "force" a test for .free callback. If it not
> relevant I'll remove ".free" callback of exti domain.
> As a part of this series has already been taken by Linus (pinctrl part),
> I will send a new series only for irqchip part (patches [1] and [2]). Do
> you agree ?
>

Thanks in advance
Alex

> Thanks
> Alex
>
>
>>
>> Thanks,
>>
>>     tglx
>>
>
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Hi Thomas,

On 09/14/2016 03:44 PM, Alexandre Torgue wrote:
>
>
> On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
>> On Wed, 14 Sep 2016, Alexandre Torgue wrote:
>>> On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
>>>>
>>>> Now what really bugs me is that you do that at all. An interrupt
>>>> which is
>>>> freed must be masked already. Why is it unmasked in the first place?
>>>
>>> Honestly I don't know. When "devm_free_irq" is called to release
>>> virq, there
>>> is no issue and interrupt is well masked. But, when I tried to use
>>> "irq_dispose_mapping(virq)" I observed that .free is called (child
>>> and parent
>>> domain) but interrupt is not masked.
>>
>> Well, you just used some function in some context which is not
>> relevant to
>> the normal operation. So adding that mask() is just paranoia for no
>> value.
>
A gentle reminder ping...
If ".free" callback is not relevant then I 'll remove it from exti domain.

> I agree. I just wanted to "force" a test for .free callback. If it not
> relevant I'll remove ".free" callback of exti domain.
> As a part of this series has already been taken by Linus (pinctrl part),
> I will send a new series only for irqchip part (patches [1] and [2]). Do
> you agree ?
>

Thanks in advance
Alex

> Thanks
> Alex
>
>
>>
>> Thanks,
>>
>>     tglx
>>
>
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Hi Thomas,

On 09/14/2016 03:44 PM, Alexandre Torgue wrote:
>
>
> On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
>> On Wed, 14 Sep 2016, Alexandre Torgue wrote:
>>> On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
>>>>
>>>> Now what really bugs me is that you do that at all. An interrupt
>>>> which is
>>>> freed must be masked already. Why is it unmasked in the first place?
>>>
>>> Honestly I don't know. When "devm_free_irq" is called to release
>>> virq, there
>>> is no issue and interrupt is well masked. But, when I tried to use
>>> "irq_dispose_mapping(virq)" I observed that .free is called (child
>>> and parent
>>> domain) but interrupt is not masked.
>>
>> Well, you just used some function in some context which is not
>> relevant to
>> the normal operation. So adding that mask() is just paranoia for no
>> value.
>
A gentle reminder ping...
If ".free" callback is not relevant then I 'll remove it from exti domain.

> I agree. I just wanted to "force" a test for .free callback. If it not
> relevant I'll remove ".free" callback of exti domain.
> As a part of this series has already been taken by Linus (pinctrl part),
> I will send a new series only for irqchip part (patches [1] and [2]). Do
> you agree ?
>

Thanks in advance
Alex

> Thanks
> Alex
>
>
>>
>> Thanks,
>>
>>     tglx
>>
>
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Tue, 20 Sep 2016, Alexandre Torgue wrote:
> > On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
> > > Well, you just used some function in some context which is not
> > > relevant to
> > > the normal operation. So adding that mask() is just paranoia for no
> > > value.
> > 
> A gentle reminder ping...
> If ".free" callback is not relevant then I 'll remove it from exti domain.

I was not talking about the .free callback in general. I was talking about
the masking. But yes, if the thing is otherwise a NOOP, then you can spare
it completely.

Thanks,

	tglx

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Tue, 20 Sep 2016, Alexandre Torgue wrote:
> > On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
> > > Well, you just used some function in some context which is not
> > > relevant to
> > > the normal operation. So adding that mask() is just paranoia for no
> > > value.
> > 
> A gentle reminder ping...
> If ".free" callback is not relevant then I 'll remove it from exti domain.

I was not talking about the .free callback in general. I was talking about
the masking. But yes, if the thing is otherwise a NOOP, then you can spare
it completely.

Thanks,

	tglx

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Thomas,

On 09/20/2016 11:51 AM, Thomas Gleixner wrote:
> On Tue, 20 Sep 2016, Alexandre Torgue wrote:
>>> On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
>>>> Well, you just used some function in some context which is not
>>>> relevant to
>>>> the normal operation. So adding that mask() is just paranoia for no
>>>> value.
>>>
>> A gentle reminder ping...
>> If ".free" callback is not relevant then I 'll remove it from exti domain.

Sorry for discussing about the same thing again (and again) but I just 
want to be sure before sending a new version. As you know I have 2 
domains: EXTI domain (parent) and stm32-pinctrl-bank domain (child one).

There does it make sens to have ".free" callbacks defined in both domain 
(actually if I define one for the child domain I have to define also 
".free" callback for parent domain (EXTI) as it is hierarchical) ?
If ".free" have no chance to be called then I will send a new version by 
removing .free callbacks (in both domain).

Regards
Alex

>
> I was not talking about the .free callback in general. I was talking about
> the masking. But yes, if the thing is otherwise a NOOP, then you can spare
> it completely.
>
> Thanks,
>
> 	tglx
>

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Thomas,

On 09/20/2016 11:51 AM, Thomas Gleixner wrote:
> On Tue, 20 Sep 2016, Alexandre Torgue wrote:
>>> On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
>>>> Well, you just used some function in some context which is not
>>>> relevant to
>>>> the normal operation. So adding that mask() is just paranoia for no
>>>> value.
>>>
>> A gentle reminder ping...
>> If ".free" callback is not relevant then I 'll remove it from exti domain.

Sorry for discussing about the same thing again (and again) but I just 
want to be sure before sending a new version. As you know I have 2 
domains: EXTI domain (parent) and stm32-pinctrl-bank domain (child one).

There does it make sens to have ".free" callbacks defined in both domain 
(actually if I define one for the child domain I have to define also 
".free" callback for parent domain (EXTI) as it is hierarchical) ?
If ".free" have no chance to be called then I will send a new version by 
removing .free callbacks (in both domain).

Regards
Alex

>
> I was not talking about the .free callback in general. I was talking about
> the masking. But yes, if the thing is otherwise a NOOP, then you can spare
> it completely.
>
> Thanks,
>
> 	tglx
>

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Thomas,

On 09/20/2016 11:51 AM, Thomas Gleixner wrote:
> On Tue, 20 Sep 2016, Alexandre Torgue wrote:
>>> On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
>>>> Well, you just used some function in some context which is not
>>>> relevant to
>>>> the normal operation. So adding that mask() is just paranoia for no
>>>> value.
>>>
>> A gentle reminder ping...
>> If ".free" callback is not relevant then I 'll remove it from exti domain.

Sorry for discussing about the same thing again (and again) but I just 
want to be sure before sending a new version. As you know I have 2 
domains: EXTI domain (parent) and stm32-pinctrl-bank domain (child one).

There does it make sens to have ".free" callbacks defined in both domain 
(actually if I define one for the child domain I have to define also 
".free" callback for parent domain (EXTI) as it is hierarchical) ?
If ".free" have no chance to be called then I will send a new version by 
removing .free callbacks (in both domain).

Regards
Alex

>
> I was not talking about the .free callback in general. I was talking about
> the masking. But yes, if the thing is otherwise a NOOP, then you can spare
> it completely.
>
> Thanks,
>
> 	tglx
>

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Tue, 20 Sep 2016, Alexandre Torgue wrote:

> Thomas,
> 
> On 09/20/2016 11:51 AM, Thomas Gleixner wrote:
> > On Tue, 20 Sep 2016, Alexandre Torgue wrote:
> > > > On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
> > > > > Well, you just used some function in some context which is not
> > > > > relevant to
> > > > > the normal operation. So adding that mask() is just paranoia for no
> > > > > value.
> > > > 
> > > A gentle reminder ping...
> > > If ".free" callback is not relevant then I 'll remove it from exti domain.
> 
> Sorry for discussing about the same thing again (and again) but I just want to
> be sure before sending a new version. As you know I have 2 domains: EXTI
> domain (parent) and stm32-pinctrl-bank domain (child one).
> 
> There does it make sens to have ".free" callbacks defined in both domain
> (actually if I define one for the child domain I have to define also ".free"
> callback for parent domain (EXTI) as it is hierarchical) ?
> If ".free" have no chance to be called then I will send a new version by
> removing .free callbacks (in both domain).

Free will be called when a interrupt in the child domain is torn down,
i.e. when irq_domain_free_irqs() is called. And it will be called for both
domains like the alloc callback is invoked on both domains via
irq_domain_alloc_irqs().

Thanks,

	tglx

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Tue, 20 Sep 2016, Alexandre Torgue wrote:

> Thomas,
> 
> On 09/20/2016 11:51 AM, Thomas Gleixner wrote:
> > On Tue, 20 Sep 2016, Alexandre Torgue wrote:
> > > > On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
> > > > > Well, you just used some function in some context which is not
> > > > > relevant to
> > > > > the normal operation. So adding that mask() is just paranoia for no
> > > > > value.
> > > > 
> > > A gentle reminder ping...
> > > If ".free" callback is not relevant then I 'll remove it from exti domain.
> 
> Sorry for discussing about the same thing again (and again) but I just want to
> be sure before sending a new version. As you know I have 2 domains: EXTI
> domain (parent) and stm32-pinctrl-bank domain (child one).
> 
> There does it make sens to have ".free" callbacks defined in both domain
> (actually if I define one for the child domain I have to define also ".free"
> callback for parent domain (EXTI) as it is hierarchical) ?
> If ".free" have no chance to be called then I will send a new version by
> removing .free callbacks (in both domain).

Free will be called when a interrupt in the child domain is torn down,
i.e. when irq_domain_free_irqs() is called. And it will be called for both
domains like the alloc callback is invoked on both domains via
irq_domain_alloc_irqs().

Thanks,

	tglx

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Thomas,

On 09/20/2016 02:44 PM, Thomas Gleixner wrote:
> On Tue, 20 Sep 2016, Alexandre Torgue wrote:
>
>> Thomas,
>>
>> On 09/20/2016 11:51 AM, Thomas Gleixner wrote:
>>> On Tue, 20 Sep 2016, Alexandre Torgue wrote:
>>>>> On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
>>>>>> Well, you just used some function in some context which is not
>>>>>> relevant to
>>>>>> the normal operation. So adding that mask() is just paranoia for no
>>>>>> value.
>>>>>
>>>> A gentle reminder ping...
>>>> If ".free" callback is not relevant then I 'll remove it from exti domain.
>>
>> Sorry for discussing about the same thing again (and again) but I just want to
>> be sure before sending a new version. As you know I have 2 domains: EXTI
>> domain (parent) and stm32-pinctrl-bank domain (child one).
>>
>> There does it make sens to have ".free" callbacks defined in both domain
>> (actually if I define one for the child domain I have to define also ".free"
>> callback for parent domain (EXTI) as it is hierarchical) ?
>> If ".free" have no chance to be called then I will send a new version by
>> removing .free callbacks (in both domain).
>
> Free will be called when a interrupt in the child domain is torn down,
> i.e. when irq_domain_free_irqs() is called. And it will be called for both
> domains like the alloc callback is invoked on both domains via
> irq_domain_alloc_irqs().

Thanks Thomas for this clarification (I'm sure now that we need .free 
callbacks).
irq_domain_free_irqs() is called in 2 scenario:
1- when issue occurs in irq_create_fwspec_mapping()
2- when irq_dispose_mapping() is called

Case 2 is the one I tested some times ago. In this case, I need to mask 
interrupts in .free callback of EXTI (parent) domain to avoid spurious 
interrupts.

Regards

Alex


>
> Thanks,
>
> 	tglx
>
>
>
>

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Thomas,

On 09/20/2016 02:44 PM, Thomas Gleixner wrote:
> On Tue, 20 Sep 2016, Alexandre Torgue wrote:
>
>> Thomas,
>>
>> On 09/20/2016 11:51 AM, Thomas Gleixner wrote:
>>> On Tue, 20 Sep 2016, Alexandre Torgue wrote:
>>>>> On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
>>>>>> Well, you just used some function in some context which is not
>>>>>> relevant to
>>>>>> the normal operation. So adding that mask() is just paranoia for no
>>>>>> value.
>>>>>
>>>> A gentle reminder ping...
>>>> If ".free" callback is not relevant then I 'll remove it from exti domain.
>>
>> Sorry for discussing about the same thing again (and again) but I just want to
>> be sure before sending a new version. As you know I have 2 domains: EXTI
>> domain (parent) and stm32-pinctrl-bank domain (child one).
>>
>> There does it make sens to have ".free" callbacks defined in both domain
>> (actually if I define one for the child domain I have to define also ".free"
>> callback for parent domain (EXTI) as it is hierarchical) ?
>> If ".free" have no chance to be called then I will send a new version by
>> removing .free callbacks (in both domain).
>
> Free will be called when a interrupt in the child domain is torn down,
> i.e. when irq_domain_free_irqs() is called. And it will be called for both
> domains like the alloc callback is invoked on both domains via
> irq_domain_alloc_irqs().

Thanks Thomas for this clarification (I'm sure now that we need .free 
callbacks).
irq_domain_free_irqs() is called in 2 scenario:
1- when issue occurs in irq_create_fwspec_mapping()
2- when irq_dispose_mapping() is called

Case 2 is the one I tested some times ago. In this case, I need to mask 
interrupts in .free callback of EXTI (parent) domain to avoid spurious 
interrupts.

Regards

Alex


>
> Thanks,
>
> 	tglx
>
>
>
>

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Thomas,

On 09/20/2016 02:44 PM, Thomas Gleixner wrote:
> On Tue, 20 Sep 2016, Alexandre Torgue wrote:
>
>> Thomas,
>>
>> On 09/20/2016 11:51 AM, Thomas Gleixner wrote:
>>> On Tue, 20 Sep 2016, Alexandre Torgue wrote:
>>>>> On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
>>>>>> Well, you just used some function in some context which is not
>>>>>> relevant to
>>>>>> the normal operation. So adding that mask() is just paranoia for no
>>>>>> value.
>>>>>
>>>> A gentle reminder ping...
>>>> If ".free" callback is not relevant then I 'll remove it from exti domain.
>>
>> Sorry for discussing about the same thing again (and again) but I just want to
>> be sure before sending a new version. As you know I have 2 domains: EXTI
>> domain (parent) and stm32-pinctrl-bank domain (child one).
>>
>> There does it make sens to have ".free" callbacks defined in both domain
>> (actually if I define one for the child domain I have to define also ".free"
>> callback for parent domain (EXTI) as it is hierarchical) ?
>> If ".free" have no chance to be called then I will send a new version by
>> removing .free callbacks (in both domain).
>
> Free will be called when a interrupt in the child domain is torn down,
> i.e. when irq_domain_free_irqs() is called. And it will be called for both
> domains like the alloc callback is invoked on both domains via
> irq_domain_alloc_irqs().

Thanks Thomas for this clarification (I'm sure now that we need .free 
callbacks).
irq_domain_free_irqs() is called in 2 scenario:
1- when issue occurs in irq_create_fwspec_mapping()
2- when irq_dispose_mapping() is called

Case 2 is the one I tested some times ago. In this case, I need to mask 
interrupts in .free callback of EXTI (parent) domain to avoid spurious 
interrupts.

Regards

Alex


>
> Thanks,
>
> 	tglx
>
>
>
>

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Tue, 20 Sep 2016, Alexandre Torgue wrote:
> On 09/20/2016 02:44 PM, Thomas Gleixner wrote:
> > Free will be called when a interrupt in the child domain is torn down,
> > i.e. when irq_domain_free_irqs() is called. And it will be called for both
> > domains like the alloc callback is invoked on both domains via
> > irq_domain_alloc_irqs().
> 
> Thanks Thomas for this clarification (I'm sure now that we need .free
> callbacks).
> irq_domain_free_irqs() is called in 2 scenario:
> 1- when issue occurs in irq_create_fwspec_mapping()
> 2- when irq_dispose_mapping() is called
> 
> Case 2 is the one I tested some times ago. In this case, I need to mask
> interrupts in .free callback of EXTI (parent) domain to avoid spurious
> interrupts.

And why would irq_dispose_mapping() be called on an unmasked, i.e. active,
interrupt? The masking is just papering over that.

Thanks,

	tglx

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Tue, 20 Sep 2016, Alexandre Torgue wrote:
> On 09/20/2016 02:44 PM, Thomas Gleixner wrote:
> > Free will be called when a interrupt in the child domain is torn down,
> > i.e. when irq_domain_free_irqs() is called. And it will be called for both
> > domains like the alloc callback is invoked on both domains via
> > irq_domain_alloc_irqs().
> 
> Thanks Thomas for this clarification (I'm sure now that we need .free
> callbacks).
> irq_domain_free_irqs() is called in 2 scenario:
> 1- when issue occurs in irq_create_fwspec_mapping()
> 2- when irq_dispose_mapping() is called
> 
> Case 2 is the one I tested some times ago. In this case, I need to mask
> interrupts in .free callback of EXTI (parent) domain to avoid spurious
> interrupts.

And why would irq_dispose_mapping() be called on an unmasked, i.e. active,
interrupt? The masking is just papering over that.

Thanks,

	tglx

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Thomas,

On 09/20/2016 04:02 PM, Thomas Gleixner wrote:
> On Tue, 20 Sep 2016, Alexandre Torgue wrote:
>> On 09/20/2016 02:44 PM, Thomas Gleixner wrote:
>>> Free will be called when a interrupt in the child domain is torn down,
>>> i.e. when irq_domain_free_irqs() is called. And it will be called for both
>>> domains like the alloc callback is invoked on both domains via
>>> irq_domain_alloc_irqs().
>>
>> Thanks Thomas for this clarification (I'm sure now that we need .free
>> callbacks).
>> irq_domain_free_irqs() is called in 2 scenario:
>> 1- when issue occurs in irq_create_fwspec_mapping()
>> 2- when irq_dispose_mapping() is called
>>
>> Case 2 is the one I tested some times ago. In this case, I need to mask
>> interrupts in .free callback of EXTI (parent) domain to avoid spurious
>> interrupts.
>
> And why would irq_dispose_mapping() be called on an unmasked, i.e. active,
> interrupt? The masking is just papering over that.

Ok. So my test was wrong and irq_dispose_mapping() has to be called when 
irq is masked (for example just  after free_irq()). For sure in this 
case the mask inside exti free callback has no sens (catch :))

I will change .free callback by:

static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
			    unsigned int nr_irqs)
{
	struct irq_data *data = irq_domain_get_irq_data(d, virq);
	irq_domain_reset_irq_data(data);
}


so if you agree I will resend only patches concerning stm32 exti driver 
[1],[2],[3],[4]

Thanks for your time.

alex


>
> Thanks,
>
> 	tglx
>

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Thomas,

On 09/20/2016 04:02 PM, Thomas Gleixner wrote:
> On Tue, 20 Sep 2016, Alexandre Torgue wrote:
>> On 09/20/2016 02:44 PM, Thomas Gleixner wrote:
>>> Free will be called when a interrupt in the child domain is torn down,
>>> i.e. when irq_domain_free_irqs() is called. And it will be called for both
>>> domains like the alloc callback is invoked on both domains via
>>> irq_domain_alloc_irqs().
>>
>> Thanks Thomas for this clarification (I'm sure now that we need .free
>> callbacks).
>> irq_domain_free_irqs() is called in 2 scenario:
>> 1- when issue occurs in irq_create_fwspec_mapping()
>> 2- when irq_dispose_mapping() is called
>>
>> Case 2 is the one I tested some times ago. In this case, I need to mask
>> interrupts in .free callback of EXTI (parent) domain to avoid spurious
>> interrupts.
>
> And why would irq_dispose_mapping() be called on an unmasked, i.e. active,
> interrupt? The masking is just papering over that.

Ok. So my test was wrong and irq_dispose_mapping() has to be called when 
irq is masked (for example just  after free_irq()). For sure in this 
case the mask inside exti free callback has no sens (catch :))

I will change .free callback by:

static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
			    unsigned int nr_irqs)
{
	struct irq_data *data = irq_domain_get_irq_data(d, virq);
	irq_domain_reset_irq_data(data);
}


so if you agree I will resend only patches concerning stm32 exti driver 
[1],[2],[3],[4]

Thanks for your time.

alex


>
> Thanks,
>
> 	tglx
>

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Thomas,

On 09/20/2016 04:02 PM, Thomas Gleixner wrote:
> On Tue, 20 Sep 2016, Alexandre Torgue wrote:
>> On 09/20/2016 02:44 PM, Thomas Gleixner wrote:
>>> Free will be called when a interrupt in the child domain is torn down,
>>> i.e. when irq_domain_free_irqs() is called. And it will be called for both
>>> domains like the alloc callback is invoked on both domains via
>>> irq_domain_alloc_irqs().
>>
>> Thanks Thomas for this clarification (I'm sure now that we need .free
>> callbacks).
>> irq_domain_free_irqs() is called in 2 scenario:
>> 1- when issue occurs in irq_create_fwspec_mapping()
>> 2- when irq_dispose_mapping() is called
>>
>> Case 2 is the one I tested some times ago. In this case, I need to mask
>> interrupts in .free callback of EXTI (parent) domain to avoid spurious
>> interrupts.
>
> And why would irq_dispose_mapping() be called on an unmasked, i.e. active,
> interrupt? The masking is just papering over that.

Ok. So my test was wrong and irq_dispose_mapping() has to be called when 
irq is masked (for example just  after free_irq()). For sure in this 
case the mask inside exti free callback has no sens (catch :))

I will change .free callback by:

static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
			    unsigned int nr_irqs)
{
	struct irq_data *data = irq_domain_get_irq_data(d, virq);
	irq_domain_reset_irq_data(data);
}


so if you agree I will resend only patches concerning stm32 exti driver 
[1],[2],[3],[4]

Thanks for your time.

alex


>
> Thanks,
>
> 	tglx
>

Re: [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Tue, 20 Sep 2016, Alexandre Torgue wrote:
> so if you agree I will resend only patches concerning stm32 exti driver
> [1],[2],[3],[4]

Ok.
 
> Thanks for your time.

Welcome,

	tglx

[PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Tue, 20 Sep 2016, Alexandre Torgue wrote:
> so if you agree I will resend only patches concerning stm32 exti driver
> [1],[2],[3],[4]

Ok.
 
> Thanks for your time.

Welcome,

	tglx

[PATCH v5 3/9] ARM: STM32: Select external interrupts controller

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2d601d7..157cea9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -877,6 +877,7 @@ config ARCH_STM32
 	select CLKSRC_STM32
 	select PINCTRL
 	select RESET_CONTROLLER
+	select STM32_EXTI
 	help
 	  Support for STMicroelectronics STM32 processors.
 
-- 
1.9.1

[PATCH v5 3/9] ARM: STM32: Select external interrupts controller

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2d601d7..157cea9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -877,6 +877,7 @@ config ARCH_STM32
 	select CLKSRC_STM32
 	select PINCTRL
 	select RESET_CONTROLLER
+	select STM32_EXTI
 	help
 	  Support for STMicroelectronics STM32 processors.
 
-- 
1.9.1

[PATCH v5 3/9] ARM: STM32: Select external interrupts controller

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2d601d7..157cea9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -877,6 +877,7 @@ config ARCH_STM32
 	select CLKSRC_STM32
 	select PINCTRL
 	select RESET_CONTROLLER
+	select STM32_EXTI
 	help
 	  Support for STMicroelectronics STM32 processors.
 
-- 
1.9.1

[PATCH v5 4/9] ARM: dts: Add EXTI controller node to stm32f429

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..1a189d4 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -176,6 +176,14 @@
 			reg = <0x40013800 0x400>;
 		};
 
+		exti: interrupt-controller@40013c00 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x40013C00 0x400>;
+			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
+		};
+
 		pin-controller {
 			#address-cells = <1>;
 			#size-cells = <1>;
-- 
1.9.1

[PATCH v5 4/9] ARM: dts: Add EXTI controller node to stm32f429

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..1a189d4 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -176,6 +176,14 @@
 			reg = <0x40013800 0x400>;
 		};
 
+		exti: interrupt-controller at 40013c00 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x40013C00 0x400>;
+			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
+		};
+
 		pin-controller {
 			#address-cells = <1>;
 			#size-cells = <1>;
-- 
1.9.1

[PATCH v5 4/9] ARM: dts: Add EXTI controller node to stm32f429

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..1a189d4 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -176,6 +176,14 @@
 			reg = <0x40013800 0x400>;
 		};
 
+		exti: interrupt-controller@40013c00 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x40013C00 0x400>;
+			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
+		};
+
 		pin-controller {
 			#address-cells = <1>;
 			#size-cells = <1>;
-- 
1.9.1

[PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index 587bffb..a0eed99 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -14,6 +14,9 @@ Required properies:
  - #size-cells	: The value of this property must be 1
  - ranges	: defines mapping between pin controller node (parent) to
    gpio-bank node (children).
+ - interrupt-parent: phandle of the interrupt parent to which the external
+   GPIO interrupts are forwarded to.
+ - st,syscfg: phandle of the syscfg node used for IRQ mux selection.
  - pins-are-numbered: Specify the subnodes are using numbered pinmux to
    specify pins.
 
-- 
1.9.1

[PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index 587bffb..a0eed99 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -14,6 +14,9 @@ Required properies:
  - #size-cells	: The value of this property must be 1
  - ranges	: defines mapping between pin controller node (parent) to
    gpio-bank node (children).
+ - interrupt-parent: phandle of the interrupt parent to which the external
+   GPIO interrupts are forwarded to.
+ - st,syscfg: phandle of the syscfg node used for IRQ mux selection.
  - pins-are-numbered: Specify the subnodes are using numbered pinmux to
    specify pins.
 
-- 
1.9.1

[PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index 587bffb..a0eed99 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -14,6 +14,9 @@ Required properies:
  - #size-cells	: The value of this property must be 1
  - ranges	: defines mapping between pin controller node (parent) to
    gpio-bank node (children).
+ - interrupt-parent: phandle of the interrupt parent to which the external
+   GPIO interrupts are forwarded to.
+ - st,syscfg: phandle of the syscfg node used for IRQ mux selection.
  - pins-are-numbered: Specify the subnodes are using numbered pinmux to
    specify pins.
 
-- 
1.9.1

Re: [PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Linus Walleij]

On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
<alexandre.torgue-qxv4g6HH51o@public.gmane.org> wrote:

> Signed-off-by: Maxime Coquelin <mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org>

Patch applied to the pinctrl tree.

I am happy with this solution.

As I see it, it doesn't hurt to add this into the pinctrl
tree while the irqchip stuff and DTS stuff get merged
into different trees orthogonally.

Yours,
Linus Walleij
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[PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Linus Walleij]

On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
<alexandre.torgue@st.com> wrote:

> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

Patch applied to the pinctrl tree.

I am happy with this solution.

As I see it, it doesn't hurt to add this into the pinctrl
tree while the irqchip stuff and DTS stuff get merged
into different trees orthogonally.

Yours,
Linus Walleij

Re: [PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Linus Walleij]

On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
<alexandre.torgue@st.com> wrote:

> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

Patch applied to the pinctrl tree.

I am happy with this solution.

As I see it, it doesn't hurt to add this into the pinctrl
tree while the irqchip stuff and DTS stuff get merged
into different trees orthogonally.

Yours,
Linus Walleij

Re: [PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Linus Walleij]

On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
<alexandre.torgue@st.com> wrote:

> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
> index 587bffb..a0eed99 100644
> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
> @@ -14,6 +14,9 @@ Required properies:
>   - #size-cells : The value of this property must be 1
>   - ranges      : defines mapping between pin controller node (parent) to
>     gpio-bank node (children).
> + - interrupt-parent: phandle of the interrupt parent to which the external
> +   GPIO interrupts are forwarded to.
> + - st,syscfg: phandle of the syscfg node used for IRQ mux selection.

Actually this doc is incomplete.

This is a phandle + offset, not just a phandle.

It is a small detail so I don't care much, either send a patch to
fix up this doc (I have already merged it) or patch the driver
to not retrieve the offset and instead use
#define SYSCFG_OFFSET 0x08
or something...

Yours,
Linus Walleij

[PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Linus Walleij]

On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
<alexandre.torgue@st.com> wrote:

> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
> index 587bffb..a0eed99 100644
> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
> @@ -14,6 +14,9 @@ Required properies:
>   - #size-cells : The value of this property must be 1
>   - ranges      : defines mapping between pin controller node (parent) to
>     gpio-bank node (children).
> + - interrupt-parent: phandle of the interrupt parent to which the external
> +   GPIO interrupts are forwarded to.
> + - st,syscfg: phandle of the syscfg node used for IRQ mux selection.

Actually this doc is incomplete.

This is a phandle + offset, not just a phandle.

It is a small detail so I don't care much, either send a patch to
fix up this doc (I have already merged it) or patch the driver
to not retrieve the offset and instead use
#define SYSCFG_OFFSET 0x08
or something...

Yours,
Linus Walleij

Re: [PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Linus Walleij]

On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
<alexandre.torgue@st.com> wrote:

> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
> index 587bffb..a0eed99 100644
> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
> @@ -14,6 +14,9 @@ Required properies:
>   - #size-cells : The value of this property must be 1
>   - ranges      : defines mapping between pin controller node (parent) to
>     gpio-bank node (children).
> + - interrupt-parent: phandle of the interrupt parent to which the external
> +   GPIO interrupts are forwarded to.
> + - st,syscfg: phandle of the syscfg node used for IRQ mux selection.

Actually this doc is incomplete.

This is a phandle + offset, not just a phandle.

It is a small detail so I don't care much, either send a patch to
fix up this doc (I have already merged it) or patch the driver
to not retrieve the offset and instead use
#define SYSCFG_OFFSET 0x08
or something...

Yours,
Linus Walleij

Re: [PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Alexandre Torgue]

Hi Linus,

On 09/13/2016 10:18 AM, Linus Walleij wrote:
> On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
> <alexandre.torgue@st.com> wrote:
>
>> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
>> Acked-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
>> index 587bffb..a0eed99 100644
>> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
>> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
>> @@ -14,6 +14,9 @@ Required properies:
>>   - #size-cells : The value of this property must be 1
>>   - ranges      : defines mapping between pin controller node (parent) to
>>     gpio-bank node (children).
>> + - interrupt-parent: phandle of the interrupt parent to which the external
>> +   GPIO interrupts are forwarded to.
>> + - st,syscfg: phandle of the syscfg node used for IRQ mux selection.
>
> Actually this doc is incomplete.
>
> This is a phandle + offset, not just a phandle.
>
> It is a small detail so I don't care much, either send a patch to
> fix up this doc (I have already merged it) or patch the driver
> to not retrieve the offset and instead use
> #define SYSCFG_OFFSET 0x08
> or something...

I'll send a patch for Documentation.
Do I need to wait  this series is officially released (4.9-rc1) or can I 
send it now ?

Regards
Alex

>
> Yours,
> Linus Walleij
>

[PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Alexandre Torgue]

Hi Linus,

On 09/13/2016 10:18 AM, Linus Walleij wrote:
> On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
> <alexandre.torgue@st.com> wrote:
>
>> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
>> Acked-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
>> index 587bffb..a0eed99 100644
>> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
>> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
>> @@ -14,6 +14,9 @@ Required properies:
>>   - #size-cells : The value of this property must be 1
>>   - ranges      : defines mapping between pin controller node (parent) to
>>     gpio-bank node (children).
>> + - interrupt-parent: phandle of the interrupt parent to which the external
>> +   GPIO interrupts are forwarded to.
>> + - st,syscfg: phandle of the syscfg node used for IRQ mux selection.
>
> Actually this doc is incomplete.
>
> This is a phandle + offset, not just a phandle.
>
> It is a small detail so I don't care much, either send a patch to
> fix up this doc (I have already merged it) or patch the driver
> to not retrieve the offset and instead use
> #define SYSCFG_OFFSET 0x08
> or something...

I'll send a patch for Documentation.
Do I need to wait  this series is officially released (4.9-rc1) or can I 
send it now ?

Regards
Alex

>
> Yours,
> Linus Walleij
>

Re: [PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Alexandre Torgue]

Hi Linus,

On 09/13/2016 10:18 AM, Linus Walleij wrote:
> On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
> <alexandre.torgue@st.com> wrote:
>
>> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
>> Acked-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
>> index 587bffb..a0eed99 100644
>> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
>> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
>> @@ -14,6 +14,9 @@ Required properies:
>>   - #size-cells : The value of this property must be 1
>>   - ranges      : defines mapping between pin controller node (parent) to
>>     gpio-bank node (children).
>> + - interrupt-parent: phandle of the interrupt parent to which the external
>> +   GPIO interrupts are forwarded to.
>> + - st,syscfg: phandle of the syscfg node used for IRQ mux selection.
>
> Actually this doc is incomplete.
>
> This is a phandle + offset, not just a phandle.
>
> It is a small detail so I don't care much, either send a patch to
> fix up this doc (I have already merged it) or patch the driver
> to not retrieve the offset and instead use
> #define SYSCFG_OFFSET 0x08
> or something...

I'll send a patch for Documentation.
Do I need to wait  this series is officially released (4.9-rc1) or can I 
send it now ?

Regards
Alex

>
> Yours,
> Linus Walleij
>

Re: [PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Linus Walleij]

On Tue, Sep 13, 2016 at 2:34 PM, Alexandre Torgue
<alexandre.torgue@st.com> wrote:

> I'll send a patch for Documentation.
> Do I need to wait  this series is officially released (4.9-rc1) or can I
> send it now ?

No just send it now, I'll apply it directly on top.

Yours,
Linus Walleij

[PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Linus Walleij]

On Tue, Sep 13, 2016 at 2:34 PM, Alexandre Torgue
<alexandre.torgue@st.com> wrote:

> I'll send a patch for Documentation.
> Do I need to wait  this series is officially released (4.9-rc1) or can I
> send it now ?

No just send it now, I'll apply it directly on top.

Yours,
Linus Walleij

Re: [PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Linus Walleij]

On Tue, Sep 13, 2016 at 2:34 PM, Alexandre Torgue
<alexandre.torgue@st.com> wrote:

> I'll send a patch for Documentation.
> Do I need to wait  this series is officially released (4.9-rc1) or can I
> send it now ?

No just send it now, I'll apply it directly on top.

Yours,
Linus Walleij

[PATCH v5 6/9] pinctrl: Add IRQ support to STM32 gpios

[Alexandre TORGUE]

This patch adds IRQ support to STM32 gpios.

The EXTI controller has 16 lines dedicated to GPIOs.
EXTI line n can be connected to only line n of one of the GPIO ports, for
example EXTI0 can be connected to either PA0, or PB0, or PC0...
This port selection is done by specifying the port number into System
Config registers.

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index 4c40dae..24bc683 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -6,6 +6,7 @@ config PINCTRL_STM32
 	select PINMUX
 	select GENERIC_PINCONF
 	select GPIOLIB
+	select MFD_SYSCON
 
 config PINCTRL_STM32F429
 	bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 4ae596b..4f01025 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -8,6 +8,8 @@
 #include <linux/clk.h>
 #include <linux/gpio/driver.h>
 #include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -20,6 +22,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
 #include <linux/reset.h>
 #include <linux/slab.h>
 
@@ -40,6 +43,7 @@
 #define STM32_GPIO_AFRH		0x24
 
 #define STM32_GPIO_PINS_PER_BANK 16
+#define STM32_GPIO_IRQ_LINE	 16
 
 #define gpio_range_to_bank(chip) \
 		container_of(chip, struct stm32_gpio_bank, range)
@@ -65,6 +69,8 @@ struct stm32_gpio_bank {
 	spinlock_t lock;
 	struct gpio_chip gpio_chip;
 	struct pinctrl_gpio_range range;
+	struct fwnode_handle *fwnode;
+	struct irq_domain *domain;
 };
 
 struct stm32_pinctrl {
@@ -77,6 +83,9 @@ struct stm32_pinctrl {
 	struct stm32_gpio_bank *banks;
 	unsigned nbanks;
 	const struct stm32_pinctrl_match_data *match_data;
+	struct irq_domain	*domain;
+	struct regmap		*regmap;
+	struct regmap_field	*irqmux[STM32_GPIO_PINS_PER_BANK];
 };
 
 static inline int stm32_gpio_pin(int gpio)
@@ -174,6 +183,20 @@ static int stm32_gpio_direction_output(struct gpio_chip *chip,
 	return 0;
 }
 
+
+static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+	struct irq_fwspec fwspec;
+
+	fwspec.fwnode = bank->fwnode;
+	fwspec.param_count = 2;
+	fwspec.param[0] = offset;
+	fwspec.param[1] = IRQ_TYPE_NONE;
+
+	return irq_create_fwspec_mapping(&fwspec);
+}
+
 static struct gpio_chip stm32_gpio_template = {
 	.request		= stm32_gpio_request,
 	.free			= stm32_gpio_free,
@@ -181,10 +204,92 @@ static struct gpio_chip stm32_gpio_template = {
 	.set			= stm32_gpio_set,
 	.direction_input	= stm32_gpio_direction_input,
 	.direction_output	= stm32_gpio_direction_output,
+	.to_irq			= stm32_gpio_to_irq,
 };
 
-/* Pinctrl functions */
+static struct irq_chip stm32_gpio_irq_chip = {
+	.name           = "stm32gpio",
+	.irq_eoi	= irq_chip_eoi_parent,
+	.irq_mask       = irq_chip_mask_parent,
+	.irq_unmask     = irq_chip_unmask_parent,
+	.irq_set_type   = irq_chip_set_type_parent,
+};
+
+static int stm32_gpio_domain_translate(struct irq_domain *d,
+				       struct irq_fwspec *fwspec,
+				       unsigned long *hwirq,
+				       unsigned int *type)
+{
+	if ((fwspec->param_count != 2) ||
+	    (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
+		return -EINVAL;
+
+	*hwirq = fwspec->param[0];
+	*type = fwspec->param[1];
+	return 0;
+}
 
+static void stm32_gpio_domain_activate(struct irq_domain *d,
+				       struct irq_data *irq_data)
+{
+	struct stm32_gpio_bank *bank = d->host_data;
+	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+
+	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->range.id);
+}
+
+static int stm32_gpio_domain_alloc(struct irq_domain *d,
+				   unsigned int virq,
+				   unsigned int nr_irqs, void *data)
+{
+	struct stm32_gpio_bank *bank = d->host_data;
+	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+	struct irq_fwspec *fwspec = data;
+	struct irq_fwspec parent_fwspec;
+	irq_hw_number_t hwirq;
+	int ret;
+
+	hwirq = fwspec->param[0];
+	parent_fwspec.fwnode = d->parent->fwnode;
+	parent_fwspec.param_count = 2;
+	parent_fwspec.param[0] = fwspec->param[0];
+	parent_fwspec.param[1] = fwspec->param[1];
+
+	irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
+				      bank);
+
+	ret = gpiochip_lock_as_irq(&bank->gpio_chip, hwirq);
+	if (ret) {
+		dev_err(pctl->dev, "Unable to configure STM32 %s%ld as IRQ\n",
+			bank->gpio_chip.label, hwirq);
+		return ret;
+	}
+
+	ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
+	if (ret)
+		gpiochip_unlock_as_irq(&bank->gpio_chip, hwirq);
+
+	return ret;
+}
+
+static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
+				   unsigned int nr_irqs)
+{
+	struct stm32_gpio_bank *bank = d->host_data;
+	struct irq_data *data = irq_get_irq_data(virq);
+
+	irq_domain_free_irqs_common(d, virq, nr_irqs);
+	gpiochip_unlock_as_irq(&bank->gpio_chip, data->hwirq);
+}
+
+static const struct irq_domain_ops stm32_gpio_domain_ops = {
+	.translate      = stm32_gpio_domain_translate,
+	.alloc          = stm32_gpio_domain_alloc,
+	.free           = stm32_gpio_domain_free,
+	.activate	= stm32_gpio_domain_activate,
+};
+
+/* Pinctrl functions */
 static struct stm32_pinctrl_group *
 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
 {
@@ -857,6 +962,17 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
 	range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK;
 	range->npins = bank->gpio_chip.ngpio;
 	range->gc = &bank->gpio_chip;
+
+	/* create irq hierarchical domain */
+	bank->fwnode = of_node_to_fwnode(np);
+
+	bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
+					STM32_GPIO_IRQ_LINE, bank->fwnode,
+					&stm32_gpio_domain_ops, bank);
+
+	if (!bank->domain)
+		return -ENODEV;
+
 	err = gpiochip_add_data(&bank->gpio_chip, bank);
 	if (err) {
 		dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
@@ -867,6 +983,47 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
 	return 0;
 }
 
+static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
+			   struct stm32_pinctrl *pctl)
+{
+	struct device_node *np = pdev->dev.of_node, *parent;
+	struct device *dev = &pdev->dev;
+	struct regmap *rm;
+	int offset, ret, i;
+
+	parent = of_irq_find_parent(np);
+	if (!parent)
+		return -ENXIO;
+
+	pctl->domain = irq_find_host(parent);
+	if (!pctl->domain)
+		return -ENXIO;
+
+	pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
+	if (IS_ERR(pctl->regmap))
+		return PTR_ERR(pctl->regmap);
+
+	rm = pctl->regmap;
+
+	ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
+		struct reg_field mux;
+
+		mux.reg = offset + (i / 4) * 4;
+		mux.lsb = (i % 4) * 4;
+		mux.msb = mux.lsb + 3;
+
+		pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
+		if (IS_ERR(pctl->irqmux[i]))
+			return PTR_ERR(pctl->irqmux[i]);
+	}
+
+	return 0;
+}
+
 static int stm32_pctrl_build_state(struct platform_device *pdev)
 {
 	struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
@@ -935,6 +1092,10 @@ int stm32_pctl_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
+	ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
+	if (ret)
+		return ret;
+
 	for_each_child_of_node(np, child)
 		if (of_property_read_bool(child, "gpio-controller"))
 			banks++;
-- 
1.9.1

[PATCH v5 6/9] pinctrl: Add IRQ support to STM32 gpios

[Alexandre TORGUE]

This patch adds IRQ support to STM32 gpios.

The EXTI controller has 16 lines dedicated to GPIOs.
EXTI line n can be connected to only line n of one of the GPIO ports, for
example EXTI0 can be connected to either PA0, or PB0, or PC0...
This port selection is done by specifying the port number into System
Config registers.

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index 4c40dae..24bc683 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -6,6 +6,7 @@ config PINCTRL_STM32
 	select PINMUX
 	select GENERIC_PINCONF
 	select GPIOLIB
+	select MFD_SYSCON
 
 config PINCTRL_STM32F429
 	bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 4ae596b..4f01025 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -8,6 +8,8 @@
 #include <linux/clk.h>
 #include <linux/gpio/driver.h>
 #include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -20,6 +22,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
 #include <linux/reset.h>
 #include <linux/slab.h>
 
@@ -40,6 +43,7 @@
 #define STM32_GPIO_AFRH		0x24
 
 #define STM32_GPIO_PINS_PER_BANK 16
+#define STM32_GPIO_IRQ_LINE	 16
 
 #define gpio_range_to_bank(chip) \
 		container_of(chip, struct stm32_gpio_bank, range)
@@ -65,6 +69,8 @@ struct stm32_gpio_bank {
 	spinlock_t lock;
 	struct gpio_chip gpio_chip;
 	struct pinctrl_gpio_range range;
+	struct fwnode_handle *fwnode;
+	struct irq_domain *domain;
 };
 
 struct stm32_pinctrl {
@@ -77,6 +83,9 @@ struct stm32_pinctrl {
 	struct stm32_gpio_bank *banks;
 	unsigned nbanks;
 	const struct stm32_pinctrl_match_data *match_data;
+	struct irq_domain	*domain;
+	struct regmap		*regmap;
+	struct regmap_field	*irqmux[STM32_GPIO_PINS_PER_BANK];
 };
 
 static inline int stm32_gpio_pin(int gpio)
@@ -174,6 +183,20 @@ static int stm32_gpio_direction_output(struct gpio_chip *chip,
 	return 0;
 }
 
+
+static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+	struct irq_fwspec fwspec;
+
+	fwspec.fwnode = bank->fwnode;
+	fwspec.param_count = 2;
+	fwspec.param[0] = offset;
+	fwspec.param[1] = IRQ_TYPE_NONE;
+
+	return irq_create_fwspec_mapping(&fwspec);
+}
+
 static struct gpio_chip stm32_gpio_template = {
 	.request		= stm32_gpio_request,
 	.free			= stm32_gpio_free,
@@ -181,10 +204,92 @@ static struct gpio_chip stm32_gpio_template = {
 	.set			= stm32_gpio_set,
 	.direction_input	= stm32_gpio_direction_input,
 	.direction_output	= stm32_gpio_direction_output,
+	.to_irq			= stm32_gpio_to_irq,
 };
 
-/* Pinctrl functions */
+static struct irq_chip stm32_gpio_irq_chip = {
+	.name           = "stm32gpio",
+	.irq_eoi	= irq_chip_eoi_parent,
+	.irq_mask       = irq_chip_mask_parent,
+	.irq_unmask     = irq_chip_unmask_parent,
+	.irq_set_type   = irq_chip_set_type_parent,
+};
+
+static int stm32_gpio_domain_translate(struct irq_domain *d,
+				       struct irq_fwspec *fwspec,
+				       unsigned long *hwirq,
+				       unsigned int *type)
+{
+	if ((fwspec->param_count != 2) ||
+	    (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
+		return -EINVAL;
+
+	*hwirq = fwspec->param[0];
+	*type = fwspec->param[1];
+	return 0;
+}
 
+static void stm32_gpio_domain_activate(struct irq_domain *d,
+				       struct irq_data *irq_data)
+{
+	struct stm32_gpio_bank *bank = d->host_data;
+	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+
+	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->range.id);
+}
+
+static int stm32_gpio_domain_alloc(struct irq_domain *d,
+				   unsigned int virq,
+				   unsigned int nr_irqs, void *data)
+{
+	struct stm32_gpio_bank *bank = d->host_data;
+	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+	struct irq_fwspec *fwspec = data;
+	struct irq_fwspec parent_fwspec;
+	irq_hw_number_t hwirq;
+	int ret;
+
+	hwirq = fwspec->param[0];
+	parent_fwspec.fwnode = d->parent->fwnode;
+	parent_fwspec.param_count = 2;
+	parent_fwspec.param[0] = fwspec->param[0];
+	parent_fwspec.param[1] = fwspec->param[1];
+
+	irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
+				      bank);
+
+	ret = gpiochip_lock_as_irq(&bank->gpio_chip, hwirq);
+	if (ret) {
+		dev_err(pctl->dev, "Unable to configure STM32 %s%ld as IRQ\n",
+			bank->gpio_chip.label, hwirq);
+		return ret;
+	}
+
+	ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
+	if (ret)
+		gpiochip_unlock_as_irq(&bank->gpio_chip, hwirq);
+
+	return ret;
+}
+
+static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
+				   unsigned int nr_irqs)
+{
+	struct stm32_gpio_bank *bank = d->host_data;
+	struct irq_data *data = irq_get_irq_data(virq);
+
+	irq_domain_free_irqs_common(d, virq, nr_irqs);
+	gpiochip_unlock_as_irq(&bank->gpio_chip, data->hwirq);
+}
+
+static const struct irq_domain_ops stm32_gpio_domain_ops = {
+	.translate      = stm32_gpio_domain_translate,
+	.alloc          = stm32_gpio_domain_alloc,
+	.free           = stm32_gpio_domain_free,
+	.activate	= stm32_gpio_domain_activate,
+};
+
+/* Pinctrl functions */
 static struct stm32_pinctrl_group *
 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
 {
@@ -857,6 +962,17 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
 	range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK;
 	range->npins = bank->gpio_chip.ngpio;
 	range->gc = &bank->gpio_chip;
+
+	/* create irq hierarchical domain */
+	bank->fwnode = of_node_to_fwnode(np);
+
+	bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
+					STM32_GPIO_IRQ_LINE, bank->fwnode,
+					&stm32_gpio_domain_ops, bank);
+
+	if (!bank->domain)
+		return -ENODEV;
+
 	err = gpiochip_add_data(&bank->gpio_chip, bank);
 	if (err) {
 		dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
@@ -867,6 +983,47 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
 	return 0;
 }
 
+static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
+			   struct stm32_pinctrl *pctl)
+{
+	struct device_node *np = pdev->dev.of_node, *parent;
+	struct device *dev = &pdev->dev;
+	struct regmap *rm;
+	int offset, ret, i;
+
+	parent = of_irq_find_parent(np);
+	if (!parent)
+		return -ENXIO;
+
+	pctl->domain = irq_find_host(parent);
+	if (!pctl->domain)
+		return -ENXIO;
+
+	pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
+	if (IS_ERR(pctl->regmap))
+		return PTR_ERR(pctl->regmap);
+
+	rm = pctl->regmap;
+
+	ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
+		struct reg_field mux;
+
+		mux.reg = offset + (i / 4) * 4;
+		mux.lsb = (i % 4) * 4;
+		mux.msb = mux.lsb + 3;
+
+		pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
+		if (IS_ERR(pctl->irqmux[i]))
+			return PTR_ERR(pctl->irqmux[i]);
+	}
+
+	return 0;
+}
+
 static int stm32_pctrl_build_state(struct platform_device *pdev)
 {
 	struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
@@ -935,6 +1092,10 @@ int stm32_pctl_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
+	ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
+	if (ret)
+		return ret;
+
 	for_each_child_of_node(np, child)
 		if (of_property_read_bool(child, "gpio-controller"))
 			banks++;
-- 
1.9.1

[PATCH v5 6/9] pinctrl: Add IRQ support to STM32 gpios

[Alexandre TORGUE]

This patch adds IRQ support to STM32 gpios.

The EXTI controller has 16 lines dedicated to GPIOs.
EXTI line n can be connected to only line n of one of the GPIO ports, for
example EXTI0 can be connected to either PA0, or PB0, or PC0...
This port selection is done by specifying the port number into System
Config registers.

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index 4c40dae..24bc683 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -6,6 +6,7 @@ config PINCTRL_STM32
 	select PINMUX
 	select GENERIC_PINCONF
 	select GPIOLIB
+	select MFD_SYSCON
 
 config PINCTRL_STM32F429
 	bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 4ae596b..4f01025 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -8,6 +8,8 @@
 #include <linux/clk.h>
 #include <linux/gpio/driver.h>
 #include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -20,6 +22,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
 #include <linux/reset.h>
 #include <linux/slab.h>
 
@@ -40,6 +43,7 @@
 #define STM32_GPIO_AFRH		0x24
 
 #define STM32_GPIO_PINS_PER_BANK 16
+#define STM32_GPIO_IRQ_LINE	 16
 
 #define gpio_range_to_bank(chip) \
 		container_of(chip, struct stm32_gpio_bank, range)
@@ -65,6 +69,8 @@ struct stm32_gpio_bank {
 	spinlock_t lock;
 	struct gpio_chip gpio_chip;
 	struct pinctrl_gpio_range range;
+	struct fwnode_handle *fwnode;
+	struct irq_domain *domain;
 };
 
 struct stm32_pinctrl {
@@ -77,6 +83,9 @@ struct stm32_pinctrl {
 	struct stm32_gpio_bank *banks;
 	unsigned nbanks;
 	const struct stm32_pinctrl_match_data *match_data;
+	struct irq_domain	*domain;
+	struct regmap		*regmap;
+	struct regmap_field	*irqmux[STM32_GPIO_PINS_PER_BANK];
 };
 
 static inline int stm32_gpio_pin(int gpio)
@@ -174,6 +183,20 @@ static int stm32_gpio_direction_output(struct gpio_chip *chip,
 	return 0;
 }
 
+
+static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+	struct irq_fwspec fwspec;
+
+	fwspec.fwnode = bank->fwnode;
+	fwspec.param_count = 2;
+	fwspec.param[0] = offset;
+	fwspec.param[1] = IRQ_TYPE_NONE;
+
+	return irq_create_fwspec_mapping(&fwspec);
+}
+
 static struct gpio_chip stm32_gpio_template = {
 	.request		= stm32_gpio_request,
 	.free			= stm32_gpio_free,
@@ -181,10 +204,92 @@ static struct gpio_chip stm32_gpio_template = {
 	.set			= stm32_gpio_set,
 	.direction_input	= stm32_gpio_direction_input,
 	.direction_output	= stm32_gpio_direction_output,
+	.to_irq			= stm32_gpio_to_irq,
 };
 
-/* Pinctrl functions */
+static struct irq_chip stm32_gpio_irq_chip = {
+	.name           = "stm32gpio",
+	.irq_eoi	= irq_chip_eoi_parent,
+	.irq_mask       = irq_chip_mask_parent,
+	.irq_unmask     = irq_chip_unmask_parent,
+	.irq_set_type   = irq_chip_set_type_parent,
+};
+
+static int stm32_gpio_domain_translate(struct irq_domain *d,
+				       struct irq_fwspec *fwspec,
+				       unsigned long *hwirq,
+				       unsigned int *type)
+{
+	if ((fwspec->param_count != 2) ||
+	    (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
+		return -EINVAL;
+
+	*hwirq = fwspec->param[0];
+	*type = fwspec->param[1];
+	return 0;
+}
 
+static void stm32_gpio_domain_activate(struct irq_domain *d,
+				       struct irq_data *irq_data)
+{
+	struct stm32_gpio_bank *bank = d->host_data;
+	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+
+	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->range.id);
+}
+
+static int stm32_gpio_domain_alloc(struct irq_domain *d,
+				   unsigned int virq,
+				   unsigned int nr_irqs, void *data)
+{
+	struct stm32_gpio_bank *bank = d->host_data;
+	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+	struct irq_fwspec *fwspec = data;
+	struct irq_fwspec parent_fwspec;
+	irq_hw_number_t hwirq;
+	int ret;
+
+	hwirq = fwspec->param[0];
+	parent_fwspec.fwnode = d->parent->fwnode;
+	parent_fwspec.param_count = 2;
+	parent_fwspec.param[0] = fwspec->param[0];
+	parent_fwspec.param[1] = fwspec->param[1];
+
+	irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
+				      bank);
+
+	ret = gpiochip_lock_as_irq(&bank->gpio_chip, hwirq);
+	if (ret) {
+		dev_err(pctl->dev, "Unable to configure STM32 %s%ld as IRQ\n",
+			bank->gpio_chip.label, hwirq);
+		return ret;
+	}
+
+	ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
+	if (ret)
+		gpiochip_unlock_as_irq(&bank->gpio_chip, hwirq);
+
+	return ret;
+}
+
+static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
+				   unsigned int nr_irqs)
+{
+	struct stm32_gpio_bank *bank = d->host_data;
+	struct irq_data *data = irq_get_irq_data(virq);
+
+	irq_domain_free_irqs_common(d, virq, nr_irqs);
+	gpiochip_unlock_as_irq(&bank->gpio_chip, data->hwirq);
+}
+
+static const struct irq_domain_ops stm32_gpio_domain_ops = {
+	.translate      = stm32_gpio_domain_translate,
+	.alloc          = stm32_gpio_domain_alloc,
+	.free           = stm32_gpio_domain_free,
+	.activate	= stm32_gpio_domain_activate,
+};
+
+/* Pinctrl functions */
 static struct stm32_pinctrl_group *
 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
 {
@@ -857,6 +962,17 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
 	range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK;
 	range->npins = bank->gpio_chip.ngpio;
 	range->gc = &bank->gpio_chip;
+
+	/* create irq hierarchical domain */
+	bank->fwnode = of_node_to_fwnode(np);
+
+	bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
+					STM32_GPIO_IRQ_LINE, bank->fwnode,
+					&stm32_gpio_domain_ops, bank);
+
+	if (!bank->domain)
+		return -ENODEV;
+
 	err = gpiochip_add_data(&bank->gpio_chip, bank);
 	if (err) {
 		dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
@@ -867,6 +983,47 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
 	return 0;
 }
 
+static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
+			   struct stm32_pinctrl *pctl)
+{
+	struct device_node *np = pdev->dev.of_node, *parent;
+	struct device *dev = &pdev->dev;
+	struct regmap *rm;
+	int offset, ret, i;
+
+	parent = of_irq_find_parent(np);
+	if (!parent)
+		return -ENXIO;
+
+	pctl->domain = irq_find_host(parent);
+	if (!pctl->domain)
+		return -ENXIO;
+
+	pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
+	if (IS_ERR(pctl->regmap))
+		return PTR_ERR(pctl->regmap);
+
+	rm = pctl->regmap;
+
+	ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
+		struct reg_field mux;
+
+		mux.reg = offset + (i / 4) * 4;
+		mux.lsb = (i % 4) * 4;
+		mux.msb = mux.lsb + 3;
+
+		pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
+		if (IS_ERR(pctl->irqmux[i]))
+			return PTR_ERR(pctl->irqmux[i]);
+	}
+
+	return 0;
+}
+
 static int stm32_pctrl_build_state(struct platform_device *pdev)
 {
 	struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
@@ -935,6 +1092,10 @@ int stm32_pctl_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
+	ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
+	if (ret)
+		return ret;
+
 	for_each_child_of_node(np, child)
 		if (of_property_read_bool(child, "gpio-controller"))
 			banks++;
-- 
1.9.1

Re: [PATCH v5 6/9] pinctrl: Add IRQ support to STM32 gpios

[Linus Walleij]

On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
<alexandre.torgue-qxv4g6HH51o@public.gmane.org> wrote:

> This patch adds IRQ support to STM32 gpios.
>
> The EXTI controller has 16 lines dedicated to GPIOs.
> EXTI line n can be connected to only line n of one of the GPIO ports, for
> example EXTI0 can be connected to either PA0, or PB0, or PC0...
> This port selection is done by specifying the port number into System
> Config registers.
>
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org>

Nicely isolated from the other irq stuff and abstracted.

It's complex but this is as clean as we can make it,
thanks for your efforts.

Patch applied.

Yours,
Linus Walleij
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[PATCH v5 6/9] pinctrl: Add IRQ support to STM32 gpios

[Linus Walleij]

On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
<alexandre.torgue@st.com> wrote:

> This patch adds IRQ support to STM32 gpios.
>
> The EXTI controller has 16 lines dedicated to GPIOs.
> EXTI line n can be connected to only line n of one of the GPIO ports, for
> example EXTI0 can be connected to either PA0, or PB0, or PC0...
> This port selection is done by specifying the port number into System
> Config registers.
>
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

Nicely isolated from the other irq stuff and abstracted.

It's complex but this is as clean as we can make it,
thanks for your efforts.

Patch applied.

Yours,
Linus Walleij

Re: [PATCH v5 6/9] pinctrl: Add IRQ support to STM32 gpios

[Linus Walleij]

On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
<alexandre.torgue@st.com> wrote:

> This patch adds IRQ support to STM32 gpios.
>
> The EXTI controller has 16 lines dedicated to GPIOs.
> EXTI line n can be connected to only line n of one of the GPIO ports, for
> example EXTI0 can be connected to either PA0, or PB0, or PC0...
> This port selection is done by specifying the port number into System
> Config registers.
>
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

Nicely isolated from the other irq stuff and abstracted.

It's complex but this is as clean as we can make it,
thanks for your efforts.

Patch applied.

Yours,
Linus Walleij

[PATCH v5 7/9] ARM: dts: Add GPIO irq support to STM2F429

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 1a189d4..6824762 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -189,6 +189,8 @@
 			#size-cells = <1>;
 			compatible = "st,stm32f429-pinctrl";
 			ranges = <0 0x40020000 0x3000>;
+			interrupt-parent = <&exti>;
+			st,syscfg = <&syscfg 0x8>;
 			pins-are-numbered;
 
 			gpioa: gpio@40020000 {
-- 
1.9.1

[PATCH v5 7/9] ARM: dts: Add GPIO irq support to STM2F429

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 1a189d4..6824762 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -189,6 +189,8 @@
 			#size-cells = <1>;
 			compatible = "st,stm32f429-pinctrl";
 			ranges = <0 0x40020000 0x3000>;
+			interrupt-parent = <&exti>;
+			st,syscfg = <&syscfg 0x8>;
 			pins-are-numbered;
 
 			gpioa: gpio at 40020000 {
-- 
1.9.1

[PATCH v5 7/9] ARM: dts: Add GPIO irq support to STM2F429

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 1a189d4..6824762 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -189,6 +189,8 @@
 			#size-cells = <1>;
 			compatible = "st,stm32f429-pinctrl";
 			ranges = <0 0x40020000 0x3000>;
+			interrupt-parent = <&exti>;
+			st,syscfg = <&syscfg 0x8>;
 			pins-are-numbered;
 
 			gpioa: gpio@40020000 {
-- 
1.9.1

[PATCH v5 8/9] ARM: dts: Declare push button as GPIO key on stm32f429 boards

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org>

diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 6bfc595..0fd78e4 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -47,6 +47,7 @@
 
 /dts-v1/;
 #include "stm32f429.dtsi"
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "STMicroelectronics STM32429i-EVAL board";
@@ -82,6 +83,23 @@
 		};
 	};
 
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+		button@0 {
+			label = "Wake up";
+			linux,code = <KEY_WAKEUP>;
+			gpios = <&gpioa 0 0>;
+		};
+		button@1 {
+			label = "Tamper";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpioc 13 0>;
+		};
+	};
+
 	usbotg_hs_phy: usbphy {
 		#phy-cells = <0>;
 		compatible = "usb-nop-xceiv";
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 0140807..7d0415e 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -47,6 +47,7 @@
 
 /dts-v1/;
 #include "stm32f429.dtsi"
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "STMicroelectronics STM32F429i-DISCO board";
@@ -75,6 +76,18 @@
 			linux,default-trigger = "heartbeat";
 		};
 	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+		button@0 {
+			label = "User";
+			linux,code = <KEY_HOME>;
+			gpios = <&gpioa 0 0>;
+		};
+	};
 };
 
 &clk_hse {
-- 
1.9.1

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[PATCH v5 8/9] ARM: dts: Declare push button as GPIO key on stm32f429 boards

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 6bfc595..0fd78e4 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -47,6 +47,7 @@
 
 /dts-v1/;
 #include "stm32f429.dtsi"
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "STMicroelectronics STM32429i-EVAL board";
@@ -82,6 +83,23 @@
 		};
 	};
 
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+		button at 0 {
+			label = "Wake up";
+			linux,code = <KEY_WAKEUP>;
+			gpios = <&gpioa 0 0>;
+		};
+		button at 1 {
+			label = "Tamper";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpioc 13 0>;
+		};
+	};
+
 	usbotg_hs_phy: usbphy {
 		#phy-cells = <0>;
 		compatible = "usb-nop-xceiv";
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 0140807..7d0415e 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -47,6 +47,7 @@
 
 /dts-v1/;
 #include "stm32f429.dtsi"
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "STMicroelectronics STM32F429i-DISCO board";
@@ -75,6 +76,18 @@
 			linux,default-trigger = "heartbeat";
 		};
 	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+		button at 0 {
+			label = "User";
+			linux,code = <KEY_HOME>;
+			gpios = <&gpioa 0 0>;
+		};
+	};
 };
 
 &clk_hse {
-- 
1.9.1

[PATCH v5 8/9] ARM: dts: Declare push button as GPIO key on stm32f429 boards

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 6bfc595..0fd78e4 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -47,6 +47,7 @@
 
 /dts-v1/;
 #include "stm32f429.dtsi"
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "STMicroelectronics STM32429i-EVAL board";
@@ -82,6 +83,23 @@
 		};
 	};
 
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+		button@0 {
+			label = "Wake up";
+			linux,code = <KEY_WAKEUP>;
+			gpios = <&gpioa 0 0>;
+		};
+		button@1 {
+			label = "Tamper";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpioc 13 0>;
+		};
+	};
+
 	usbotg_hs_phy: usbphy {
 		#phy-cells = <0>;
 		compatible = "usb-nop-xceiv";
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 0140807..7d0415e 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -47,6 +47,7 @@
 
 /dts-v1/;
 #include "stm32f429.dtsi"
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "STMicroelectronics STM32F429i-DISCO board";
@@ -75,6 +76,18 @@
 			linux,default-trigger = "heartbeat";
 		};
 	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+		button@0 {
+			label = "User";
+			linux,code = <KEY_HOME>;
+			gpios = <&gpioa 0 0>;
+		};
+	};
 };
 
 &clk_hse {
-- 
1.9.1

[PATCH v5 9/9] ARM: config: Enable GPIO Key driver in stm32_defconfig

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 1e5ec2a..e7b56d4 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -38,7 +38,11 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_BLK_DEV is not set
 CONFIG_EEPROM_93CX6=y
-# CONFIG_INPUT is not set
+# CONFIG_INPUT_LEDS is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
 # CONFIG_UNIX98_PTYS is not set
-- 
1.9.1

[PATCH v5 9/9] ARM: config: Enable GPIO Key driver in stm32_defconfig

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 1e5ec2a..e7b56d4 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -38,7 +38,11 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_BLK_DEV is not set
 CONFIG_EEPROM_93CX6=y
-# CONFIG_INPUT is not set
+# CONFIG_INPUT_LEDS is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
 # CONFIG_UNIX98_PTYS is not set
-- 
1.9.1

[PATCH v5 9/9] ARM: config: Enable GPIO Key driver in stm32_defconfig

[Alexandre TORGUE]

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 1e5ec2a..e7b56d4 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -38,7 +38,11 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_BLK_DEV is not set
 CONFIG_EEPROM_93CX6=y
-# CONFIG_INPUT is not set
+# CONFIG_INPUT_LEDS is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
 # CONFIG_UNIX98_PTYS is not set
-- 
1.9.1