From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36235) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bjKwi-0001v5-Eo for qemu-devel@nongnu.org; Mon, 12 Sep 2016 02:42:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bjKwd-0004B9-DE for qemu-devel@nongnu.org; Mon, 12 Sep 2016 02:42:24 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:39724 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bjKwd-0004As-8E for qemu-devel@nongnu.org; Mon, 12 Sep 2016 02:42:19 -0400 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u8C6bufV133705 for ; Mon, 12 Sep 2016 02:42:19 -0400 Received: from e28smtp04.in.ibm.com (e28smtp04.in.ibm.com [125.16.236.4]) by mx0b-001b2d01.pphosted.com with ESMTP id 25cec77je6-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 12 Sep 2016 02:42:18 -0400 Received: from localhost by e28smtp04.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 12 Sep 2016 12:12:14 +0530 From: Nikunj A Dadhania Date: Mon, 12 Sep 2016 12:11:40 +0530 In-Reply-To: <1473662506-27441-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1473662506-27441-1-git-send-email-nikunj@linux.vnet.ibm.com> Message-Id: <1473662506-27441-12-git-send-email-nikunj@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH RESEND v2 11/17] target-ppc: implement darn instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, benh@kernel.crashing.org, Ravi Bangoria From: Ravi Bangoria darn: Deliver A Random Number Currently return invalid random number for all the case. This needs proper algorithm to provide cryptographically suitable random data. Reading from /dev/random can block and that is not an expected behaviour while the cpu instruction is getting executed. Moreover, /dev/random would only work for linux-user Signed-off-by: Ravi Bangoria Signed-off-by: Nikunj A Dadhania --- target-ppc/helper.h | 2 ++ target-ppc/int_helper.c | 16 ++++++++++++++++ target-ppc/translate.c | 18 ++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index e75d070..966f2ce 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -50,6 +50,8 @@ DEF_HELPER_FLAGS_1(cnttzd, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_3(srad, tl, env, tl, tl) +DEF_HELPER_0(darn32, tl) +DEF_HELPER_0(darn64, tl) #endif DEF_HELPER_FLAGS_1(cntlsw32, TCG_CALL_NO_RWG_SE, i32, i32) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 291fba0..51a9ac5 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -182,6 +182,22 @@ target_ulong helper_cnttzd(target_ulong t) { return ctz64(t); } + +/* Return invalid random number. + * + * FIXME: Add rng backend or other mechanism to get cryptographically suitable + * random number + */ +target_ulong helper_darn32(void) +{ + return -1; +} + +target_ulong helper_darn64(void) +{ + return -1; +} + #endif #if defined(TARGET_PPC64) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 133c531..e9dad3f 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -528,6 +528,8 @@ EXTRACT_HELPER(FPW, 16, 1); /* addpcis */ EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0) +/* darn */ +EXTRACT_HELPER(L, 16, 2); /*** Jump target decoding ***/ /* Immediate address */ @@ -1895,6 +1897,21 @@ static void gen_cnttzd(DisasContext *ctx) gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); } } + +/* darn */ +static void gen_darn(DisasContext *ctx) +{ + int l = L(ctx->opcode); + + if (l == 0) { + gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); + } else if (l <= 2) { + /* Return 64-bit random for both CRN and RRN */ + gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); + } else { + tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); + } +} #endif /*** Integer rotate ***/ @@ -6212,6 +6229,7 @@ GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), #endif -- 2.7.4