From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com ([134.134.136.31]:14687 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932484AbcINAit (ORCPT ); Tue, 13 Sep 2016 20:38:49 -0400 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni , stable@vger.kernel.org, Tvrtko Ursulin Subject: [PATCH 7/9] drm/i915/gen9: fix the watermark res_blocks value Date: Tue, 13 Sep 2016 21:38:20 -0300 Message-Id: <1473813502-16844-8-git-send-email-paulo.r.zanoni@intel.com> In-Reply-To: <1473813502-16844-1-git-send-email-paulo.r.zanoni@intel.com> References: <1473813502-16844-1-git-send-email-paulo.r.zanoni@intel.com> Sender: stable-owner@vger.kernel.org List-ID: We forgot the "res_blocks += y_tile_minimum" that's described on step V of our documentation. Again, this should only affect the Y tiling cases. It looks like the relevant code was introduced in 0fda65680e92, but there's always the possibility that it matched our specification when it was introduced, and then the specification changed while the code stayed the same. So we can't really say this was a regression, but let's try to add a "Fixes" tag anyway to help backporting. v2: Try to add a "Fixes" tag (Maarten). Fixes: 0fda65680e92 ("drm/i915/skl: Update watermarks for Y tiling") Cc: stable@vger.kernel.org Cc: Tvrtko Ursulin Reviewed-by: Lyude Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8eae4e2..2e6099b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3561,7 +3561,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, uint8_t cpp; uint32_t width = 0, height = 0; uint32_t plane_pixel_rate; - uint32_t y_min_scanlines; + uint32_t y_tile_minimum, y_min_scanlines; if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) { *enabled = false; @@ -3618,10 +3618,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, latency, plane_blocks_per_line); + y_tile_minimum = plane_blocks_per_line * y_min_scanlines; + if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) { - uint32_t y_tile_minimum = plane_blocks_per_line * - y_min_scanlines; selected_result = max(method2, y_tile_minimum); } else { if ((ddb_allocation / plane_blocks_per_line) >= 1) @@ -3635,10 +3635,12 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, if (level >= 1 && level <= 7) { if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || - fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) + fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) { + res_blocks += y_tile_minimum; res_lines += y_min_scanlines; - else + } else { res_blocks++; + } } if (res_blocks >= ddb_allocation || res_lines > 31) { -- 2.7.4