From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37822) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkx2v-0004e5-4c for qemu-devel@nongnu.org; Fri, 16 Sep 2016 13:35:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bkx2s-0008ED-F2 for qemu-devel@nongnu.org; Fri, 16 Sep 2016 13:35:29 -0400 Received: from g2t2355.austin.hpe.com ([15.233.44.28]:57913) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkx2s-0008BX-9D for qemu-devel@nongnu.org; Fri, 16 Sep 2016 13:35:26 -0400 From: Thomas Hanson Date: Fri, 16 Sep 2016 11:34:44 -0600 Message-Id: <1474047287-145701-1-git-send-email-thomas.hanson@linaro.org> Subject: [Qemu-devel] [PATCH 0/3] tareget-arm: Handle tagged addresses when loading PC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, grant.likely@hpe.com, thomas.hanson@linaro.org If tagged addresses are enabled, then addresses being loaded into the PC must be cleaned up by overwriting the tag bits with either all 0's or all 1's as specified in the ARM ARM spec. The decision process is dependent on whether the code will be running in EL0/1 or in EL2/3 and is controlled by a combination of Top Byte Ignored (TBI) bits in the TCR and the value of bit 55 in the address being loaded. TBI values are extracted from the appropriate TCR and made available to TCG code generation routines by inserting them into the TB flags field and then transferring them to DisasContext structure in gen_intermediate_code_a64(). New function gen_a64_set_pc_reg() encapsulates the logic required to determine whether clean up of the tag byte is required and then generating the code to correctly load the PC. In addition to those instruction which can directly load a tagged address into the PC, there are others which increment or add a value to the PC. If 56 bit addressing is used, these instructions can cause an arithmetic roll-over into the tag bits. The ARM ARM specification for handling tagged addresses requires that these cases also be addressed by cleaning up the tag field. This work has been deferred because there is currently no CPU model available for testing with 56 bit addresses. Thomas Hanson (3): target-arm: Infrastucture changes to enable handling of tagged address loading into PC target-arm: Code changes to implement overwrite of tag field on PC load target-arm: Comments to mark location of pending work for 56 bit addresses target-arm/cpu.h | 20 +++++++++-- target-arm/helper.c | 42 +++++++++++++++++++++++ target-arm/translate-a64.c | 85 +++++++++++++++++++++++++++++++++++++++++----- target-arm/translate.h | 3 ++ 4 files changed, 140 insertions(+), 10 deletions(-) -- 1.9.1