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Violators will be prosecuted for from ; Wed, 28 Sep 2016 15:45:47 +1000 From: Rajalakshmi Srinivasaraghavan Date: Wed, 28 Sep 2016 11:15:15 +0530 In-Reply-To: <1475041518-9757-1-git-send-email-raji@linux.vnet.ibm.com> References: <1475041518-9757-1-git-send-email-raji@linux.vnet.ibm.com> Message-Id: <1475041518-9757-4-git-send-email-raji@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH 3/6] target-ppc: add vextu[bhw]rx instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, benh@kernel.crashing.org, "Hariharan T.S" , Avinesh Kumar , Rajalakshmi Srinivasaraghavan From: Hariharan T.S vextubrx: Vector Extract Unsigned Byte Right-Indexed VX-form vextuhrx: Vector Extract Unsigned Halfword Right-Indexed VX-form vextuwrx: Vector Extract Unsigned Word Right-Indexed VX-form Signed-off-by: Hariharan T.S. Signed-off-by: Avinesh Kumar Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h | 3 ++ target-ppc/int_helper.c | 38 ++++++++++++++++++++++++++++++++++- target-ppc/translate/vmx-impl.inc.c | 5 ++++ target-ppc/translate/vmx-ops.inc.c | 4 ++- 4 files changed, 48 insertions(+), 2 deletions(-) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 3041199..aef2f30 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -347,6 +347,9 @@ DEF_HELPER_3(vpmsumd, void, avr, avr, avr) DEF_HELPER_2(vextublx, tl, tl, avr) DEF_HELPER_2(vextuhlx, tl, tl, avr) DEF_HELPER_2(vextuwlx, tl, tl, avr) +DEF_HELPER_2(vextubrx, tl, tl, avr) +DEF_HELPER_2(vextuhrx, tl, tl, avr) +DEF_HELPER_2(vextuwrx, tl, tl, avr) DEF_HELPER_2(vsbox, void, avr, avr) DEF_HELPER_3(vcipher, void, avr, avr, avr) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index c24cc07..09a1799 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -1561,7 +1561,6 @@ void helper_vpmsumd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) #endif } - #if defined(HOST_WORDS_BIGENDIAN) #define PKBIG 1 #else @@ -1742,6 +1741,43 @@ VEXTULX_DO(vextuhlx, 2) VEXTULX_DO(vextuwlx, 4) #undef VEXTULX_DO +#if defined(HOST_WORDS_BIGENDIAN) +#define VEXTURX_DO(name, elem) \ +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \ +{ \ + target_ulong r = 0; \ + int i; \ + int index = a & 0xf; \ + for (i = elem - 1; i >= 0; i--) { \ + r = r << 8; \ + if ((15 - i - index) >= 0) { \ + r = r | b->u8[15 - i - index]; \ + } \ + } \ + return r; \ +} +#else +#define VEXTURX_DO(name, elem) \ +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \ +{ \ + target_ulong r = 0; \ + int i; \ + int index = 15 - (a & 0xf); \ + for (i = elem - 1; i >= 0; i--) { \ + r = r << 8; \ + if ((15 + i - index) <= 15) { \ + r = r | b->u8[15 + i - index]; \ + } \ + } \ + return r; \ +} +#endif + +VEXTURX_DO(vextubrx, 1) +VEXTURX_DO(vextuhrx, 2) +VEXTURX_DO(vextuwrx, 4) +#undef VEXTURX_DO + /* The specification says that the results are undefined if all of the * shift counts are not identical. We check to make sure that they are * to conform to what real hardware appears to do. */ diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c index 815ba96..10641dc 100644 --- a/target-ppc/translate/vmx-impl.inc.c +++ b/target-ppc/translate/vmx-impl.inc.c @@ -534,6 +534,11 @@ GEN_VXFORM_HETRO(vextuhlx, 6, 25) GEN_VXFORM_HETRO(vextuwlx, 6, 26) GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207, vextuwlx, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_HETRO(vextubrx, 6, 28) +GEN_VXFORM_HETRO(vextuhrx, 6, 29) +GEN_VXFORM_HETRO(vextuwrx, 6, 30) +GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \ + vextuwrx, PPC_NONE, PPC2_ISA300) #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) \ diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c index 3e0047d..87be6c6 100644 --- a/target-ppc/translate/vmx-ops.inc.c +++ b/target-ppc/translate/vmx-ops.inc.c @@ -94,7 +94,9 @@ GEN_VXFORM(vmrglw, 6, 6), GEN_VXFORM_300(vextublx, 6, 24), GEN_VXFORM_300(vextuhlx, 6, 25), GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_207(vmrgew, 6, 30), +GEN_VXFORM_300(vextubrx, 6, 28), +GEN_VXFORM_300(vextuhrx, 6, 29), +GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM(vmuloub, 4, 0), GEN_VXFORM(vmulouh, 4, 1), GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE), -- 1.7.1