From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dario Faggioli Subject: Re: [PATCH 07/24] xen: sched: don't rate limit context switches in case of yields Date: Thu, 29 Sep 2016 18:46:23 +0200 Message-ID: <1475167583.5315.33.camel@citrix.com> References: <147145358844.25877.7490417583264534196.stgit@Solace.fritz.box> <147145430260.25877.10888566175316568591.stgit@Solace.fritz.box> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1306447783790423090==" Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bpeTt-0000Rb-KB for xen-devel@lists.xenproject.org; Thu, 29 Sep 2016 16:46:45 +0000 In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: George Dunlap , xen-devel@lists.xenproject.org Cc: George Dunlap , Anshul Makkar List-Id: xen-devel@lists.xenproject.org --===============1306447783790423090== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-+17qrZWO7uRaTsVQXuMK" --=-+17qrZWO7uRaTsVQXuMK Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2016-09-20 at 14:32 +0100, George Dunlap wrote: > On 17/08/16 18:18, Dario Faggioli wrote: > > diff --git a/xen/common/sched_credit.c b/xen/common/sched_credit.c > > @@ -1771,9 +1771,18 @@ csched_schedule( > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*=C2=A0=C2=A0=C2=A0cpu and steal it= . > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > > =C2=A0 > > -=C2=A0=C2=A0=C2=A0=C2=A0/* If we have schedule rate limiting enabled, = check to see > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* how long we've run for. */ > > -=C2=A0=C2=A0=C2=A0=C2=A0if ( !tasklet_work_scheduled > > +=C2=A0=C2=A0=C2=A0=C2=A0/* > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* If we have schedule rate limiting enab= led, check to see > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* how long we've run for. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* If scurr is yielding, however, we don'= t let rate limiting > > kick in. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* In fact, it may be the case that scurr= is about to spin, > > and there's > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* no point forcing it to do so until rat= e limiting expires. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* While there, take the chance for clear= ing the yield flag at > > once. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0*/ > > +=C2=A0=C2=A0=C2=A0=C2=A0if ( !test_and_clear_bit(CSCHED_FLAG_VCPU_YIEL= D, &scurr- > > >flags) >=20 > It looks like YIELD is implemented by putting it lower in the > runqueue > in __runqueue_insert().=C2=A0=C2=A0But here you're clearing the flag befo= re the > insert happens -- won't this effectively disable yield() for credit1? >=20 Yes, I think you're right... I'm not sure how I thought it would work. :-O Thanks for pointing this out, will fix in v2. > > diff --git a/xen/common/sched_credit2.c > > b/xen/common/sched_credit2.c > > index 569174b..c8e0ee7 100644 > > --- a/xen/common/sched_credit2.c > > +++ b/xen/common/sched_credit2.c > > @@ -2267,36 +2267,40 @@ runq_candidate(struct csched2_runqueue_data > > *rqd, > > [...] > This looks good, but the code re-organization probably goes better in > the previous patch.=C2=A0=C2=A0Since you're re-sending anyway, would you = mind > moving it there? >=20 > I'm not sure the credit2 yield-ratelimit needs to be in a separate > patch; since you're implementing yield in credit2 from scratch you > could > just implement it all in one go.=C2=A0=C2=A0But since you have a patch fo= r > credit1 > anyway, I think whichever way is fine. >=20 Ok, yes, I'm moving all the Credit2 bits from this patch to the one that is actually implementing yield in Credit2 from scratch, and leaving this as the patch that makes Credit1 stop ratelimiting upon yield. Thanks and Regards, Dario --=20 <> (Raistlin Majere) ----------------------------------------------------------------- Dario Faggioli, Ph.D, http://about.me/dario.faggioli Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK) --=-+17qrZWO7uRaTsVQXuMK Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJX7UVfAAoJEBZCeImluHPu02IQALiBHONhKcoXq2R+2BugBhTc rOLlnfQCmYIA/GoLgKcIDNoTz5jSPKBx8KsnbtHZwyISC4dtKeLPAgeJKQBJ3ama pZ8mdLjGmlzxLQK+St5IqE0qHpsgbE7hon5iw8af/KMUL/g9CJWHHolo+Bwzh7kf 7/R59F+ijhyS5X6N1Bk3e70aA2MLow1Zpy/j0NSMKbZR3QrbZyh5RGGFZMM939u4 KcgC2EPmW00P46r7PL3y6H3vJ7ReGt8zmwbKS2CWUAH+fUvxtvutKWVB+A1OhhvZ HVJT7yEkCOFZM5voiXuotBBrZvbDJtvQUMpJok06grkipKMQfK+FHk+t8iQ/1QCo yNLhKcRVTB6OGXAzLuea6fr8FZTJCENCQ9+48qzybg8YSnDp7B0FRHd0Zxk7Hj8p Ed3CxTo2UC8JTaVKfUpATcqsuCTNpQlp7tda0QAmiSO67n91LHTrisFVAc4Atnm4 uRZHdsvPyHk1zM4UkpaKLcX2Jy8MWPTz0kqIY4awFACmacRQ+/qhUAeSPWO5vgtJ VdutCyWS4EEmCaHfLG5q2m5tzQbDjLH5cCzdVW70NNzeLVxddw6iePF+w9aMAV5s njzxW/5OMrClAi3mQVmKtArqo44Xbc2T0HfRrNpALMy8sUCGHckoPmIO4oUUNt78 WEfM3r7R613rWJiy0ZJo =3VpD -----END PGP SIGNATURE----- --=-+17qrZWO7uRaTsVQXuMK-- --===============1306447783790423090== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwczovL2xpc3RzLnhlbi5v cmcveGVuLWRldmVsCg== --===============1306447783790423090==--