From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43109) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bpgWi-00050g-3T for qemu-devel@nongnu.org; Thu, 29 Sep 2016 14:57:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bpgWe-0003gA-O1 for qemu-devel@nongnu.org; Thu, 29 Sep 2016 14:57:47 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46096) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bpgWe-0003fv-IH for qemu-devel@nongnu.org; Thu, 29 Sep 2016 14:57:44 -0400 From: P J P Date: Fri, 30 Sep 2016 00:27:33 +0530 Message-Id: <1475175454-3116-2-git-send-email-ppandit@redhat.com> In-Reply-To: <1475175454-3116-1-git-send-email-ppandit@redhat.com> References: <1475175454-3116-1-git-send-email-ppandit@redhat.com> Subject: [Qemu-devel] [PATCH 1/2] net: pcnet: check rx/tx descriptor ring length List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Qemu Developers Cc: Li Qiang , Jason Wang , Prasad J Pandit From: Prasad J Pandit The AMD PC-Net II emulator has set of control and status(CSR) registers. Of these, CSR76 and CSR78 hold receive and transmit descriptor ring length respectively. This ring length could range from 1 to 65535. Setting ring length to zero leads to an infinite loop in pcnet_rdra_addr. Add check to avoid it. Reported-by: Li Qiang Signed-off-by: Prasad J Pandit --- hw/net/pcnet.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/net/pcnet.c b/hw/net/pcnet.c index 198a01f..3078de8 100644 --- a/hw/net/pcnet.c +++ b/hw/net/pcnet.c @@ -1429,8 +1429,11 @@ static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value) case 47: /* POLLINT */ case 72: case 74: + break; case 76: /* RCVRL */ case 78: /* XMTRL */ + val = (val > 0) ? val : 512; + break; case 112: if (CSR_STOP(s) || CSR_SPND(s)) break; -- 2.5.5